本論文提出一組不使用 time-interleaved 架構且具備六位元解析度的高速資料
轉換器對之電路設計，並以TSMC 130nm 和 UMC 90nm 製程來實現。此類比
數位與數位類比轉換器的設計規格分別為5GS/s 和 10GS/s。在 ADC 的電路 設計當中，T/H 電路使用 capacitor-like 的 MOS 電容來消除 feedthrough noise。而比較器電路中是利用 averaging 和 interpolating 技巧來降低比較器 的offset 及輸入端的負載寄生電容。其中前置放大器是參考 active feedback 的架構，在相同的功率消耗下提升其增益頻寬積，並加入負電容進一步減少 整個電路的延遲時間。數位電路的部分則是採用CML 的邏輯閘，除了可以 降低高速轉換下容易發生的 power-ground bounce 問題也具有最高速的切換 能力。同時在 Clock 訊號路徑上加入 intentional timing skew buffers 來做 wave-pipelining，使得 Latch 能在如此高速的取樣頻率下擷取到正確的資 料。在DAC 電路設計中，Hybrid-Type Decoder 可大幅縮減邏輯閘及電流源 的數目，使其寄生電容和 Layout 複雜度降低。而輸出電流源是採用疊接方 式設計，能擁有較大的輸出阻抗。同樣為了解決訊號propagation delay 過大 的問題，在DAC 的取樣時脈訊號路徑上相同使用了 waveform pipeline 的技 巧。最後為了要能在如此高速的情況下對此晶片進行正確的量測，我們加入 DfT 機制，將 ADC 和 DAC 串接起來，可在全速下進行量測。同時並可透 過ZOH 補償之運算，推測得知此 ADC 在最遭情況下的效能表現。此組 ADC 與DAC 將應用於晶片系統內之串列傳輸鏈結。
晶片量測結果顯示，以 130nm 實現之資料轉換器對中。DAC 的 DNL 都小於±0.4LSB，INL 則不超過±0.2LSB。ADC 之 DNL 介於±0.7LSB，INL 在±0.9LSB 以內。在 3GS/s 的取樣頻率下，輸入 0.5GHz 的 sinusoidal 訊號，
輸出訊號之頻譜結果可得到38.2 dBc 的 SFDR、46.1 dB 的 SNR 的以及 36.43 dB 的 SNDR 之動態參數結果，對應到 5.76bits 的有效位元數。此組資料轉 換器對最快可操作到 3.5GS/s 的高速取樣頻率。使用的製程是 TSMC 0.13μm CMOS Mixed-Signal RF process，所佔的面積為 1.44×1.16mm2。在 supply 電壓為 1.2V 下，整個晶片總功率消耗 790mW。
而以90nm 實現之資料轉換器對的晶片量測結果顯示，DAC 的 DNL 都 小於±0.3LSB，INL 則不超過±0.2LSB。ADC 之 DNL 介於±0.6LSB，INL 在±
0.7LSB 以內。在 10GS/s 的取樣頻率下，輸入 1.1GHz 的 sinusoidal 訊號，輸 出訊號之頻譜結果可得到29.6 dBc 的 SFDR、24.2 dB 的 SNR 的以及 29.0 dB 的SNDR 之動態參數結果，對應到 3.7 bits 的有效位元數。此組資料轉換器 對在12GS/s 的取樣頻率下都還可以操作。使用的製程是 UMC 90nm CMOS Mixed-Signal Low-K process，所佔的面積為 1.21×1.1mm2。在supply 電壓為 1.0V 下，整個晶片總功率消耗 448mW。
參考文獻
[1] M. Ghoneima, Y. Ismail, M. Khellah, J. Tschanz, and V. De, “Serial-Link Bus: A Low-Power On-Chip Bus Architecture,” in Proc. IEEE/ACM International Conf.
Computer-Aided Design (ICCAD), pp. 540–545, Nov. 2005.
[2] K. Farzan, and D. A. Johns, “A CMOS 10-Gb/s Power-Efficient 4-PAM Transmitter,” IEEE J. Solid-State Circuits, vol. 39, no. 3, pp. 529 - 532, March 2004.
[3] Y. Yao, X. Yu, D. Yang, F. Dai, J.D. Irwin, and R.C. Jaeger, “A 3-Bit 20GS/s Interleaved Flash Analog-to-Digital Converter in SiGe Technology,” in Proc. IEEE Asian Solid-State Circuits Conference (A-SSCC), pp.420 - 423, Nov. 2007.
[4] P. Schvan, D. Pollex, S.C. Wang, C. Falt, and N. Ben-Hamida, “A 22GS/s 5b ADC in 0.13μm SiGe BiCMOS,” in ISSCC Digest of Technical Papers, pp. 2340 - 2349, Feb. 2006.
[5] B. Razavi, “Principles of Data Conversion System Design,” IEEE Press, 1995.
[6] David A. Johns, and Ken Martin, “Analog Integrated Circuit Design,” John Wiley
& Sons, Inc., 1997.
[7] P. E. Allen, and D. R. Holberg, “CMOS Analog Circuit Design, 2nd Edition,”
Oxford University Press, 2002.
[8] Mikael Gustavsson, J. Jacob Wikner, and Nianxiong Nick Tan, “CMOS Data Converters for Communications,” Kluwer Academic Publishers, 2000.
[9] Kent H. Lundberg, “Analog-to-Digital Converter Testing,” 2002.
[10] J. Musicer, and J. Rabaey, “MOS Current Mode Logic for Low Power, Low Noise CORDIC Computation in Mixed-Signal Environments,” in Proc. International Symposium on Low Power Electronics and Design (ISLPED), pp. 102 - 107, 2000.
[11] C. S. Vaucher, I. Ferencic, M. Locher, S. Sedvallson, U. Voegeli, and Z. Wang, “A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35-μm CMOS Technology,” IEEE J. Solid-State Circuits, vol. 35, no. 7, pp.
1039 - 1045, July 2000.
[12] M. Mizuno, M. Yamashina, K. Furuta, H. Igura, H. Abiko, K. Okabe, A. Ono, and H. Yamada, “A GHz MOS Adaptive Pipeline Technique Using MOS Current-Mode Logic,” IEEE J. Solid-State Circuits, vol. 31, no. 6, pp. 784 - 791, June 1996.
[13] W. P. Burleson, M, Ciesielski, F. Klass, and W. Liu, “Wave-Pipelining: A Tutorial and Research Survey,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 6, no. 3, pp. 464 - 474, Sep. 1998.
[14] A. G. W. Venes, and R. J. van de Plassche, “An 80-MHz, 80-mW, 8-b CMOS Folding A/D converter with Distributed Track-and-Hold Preprocessing,” IEEE J.
Solid-State Circuits, vol. 31, no. 12, pp. 1846 - 1853, Dec. 1996.
[15] P. Vorenkamp and J. Verdaasdonk, “Fully Bipolar, 120-MSample/s 10-b track-and-hold circuit,” IEEE J. Solid-State Circuits, pp. 988–992, Sept.1992.
[16] S. Shahramian, S. P. Voinigescu and A. Chan Carusone, "A 30-GS/sec Track and Hold Amplifier in 0.13-μm CMOS Technology," Custom Integrated Circuits Conference, San Jose, California, September 2006.
[17] M. Grözing, M. Berroth, E. Gerhardt, B. Franz, and W. Tempel, “High-Speed ADC Building Blocks in 90 nm CMOS, ” Fouth Joint Symposium on Opto- and Microelectronic Decices and Circuits (SODC 2006), September 02-08, 2006, Duisburg, Germany.
[18] Yu, H., Chang, and M.-C.F., "A 1V 1.25GS/S 8-bit Self-Calibrated Flash ADC in 90nm Digital CMOS", IEEE Transactions on Circuits and Systems II (TCAS-II), 55(7):668 - 672 (July 2008)
[19] E.Sackinger and W. Guggenbuhl, “A versatile building block: The CMOS differential difference amplifier, “IEEE J.Solid-State Circuits, vol.SC-22, pp.
287-294, Apr.1987.
[20] S.C Huang M.Ismail and S.R. Zarabadi, “A wide range differential difference amplifier: A basic block for analog signal processing in MOS technology, “IEEE Trans. Circuits Syst.lI, vol.40, pp.289-300, May 1993.
[21] S.-C. Liang, D.-J. Huang, C.-K. Ho, and H.-C. Hong, “10 GSamples/s, 4-bit, 1.2V, Design-for-Testability ADC and DAC in 0.13μm CMOS technology,” in Proc.
IEEE Asian Solid-State Circuits Conference (A-SSCC), pp.416 - 419, Nov. 2007.
[22] B. Razavi, “Design of Integrated Circuits for Optical Communications,” McGraw Hill, 2002.
[23] S. Galal, and B. Razavi, “10-Gb/s Limiting Amplifier and Laser/Modulator Driver in 0.18-μm CMOS Technology,” IEEE J. Solid-State Circuits, vol. 38, no. 12, pp.
2138 - 2146, Dec. 2003.
[24] E. M. Cherry, and D. E. Hooper, “The Design of Wide-Band Transistor Feedback Amplifier,” Inst. Elec. Eng. Proc., vol. 110, no. 2, pp. 375 - 389, Feb. 1963.
[25] J. A. Mataya, G. W. Haines, and S. B. Marshall, “IF amplifier using Cc compensated transistors,” IEEE J. Solid-State Circuits, vol. sc-3, no. 4, pp.
401–407, Dec. 1968.
[26] K. Kattmann and J. Barrow, “A technique for reducing differential nonlinearity errors in flash A/D converters,” in Proc. IEEE Int. Solid-State Circuits Conf. 1991, pp. 170–171.
[27] P. M. Figueiredo and J. C. Vital, “Averaging technique in flash analog-to-digital converters,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 2, pp. 233-253, Feb. 2004.
[28] K. Bult and A. Buchwald, “An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm2,” IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 1887-1895, Dec. 1997.
[29] H. Pan, M. Segami, M. Choi, J. Cao, and A. A. Abidi, “A 3.3-V 12-b 50-MS/s A/D converter in 0.6-mm CMOS with over 80-dB SFDR,” IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1769-1780, Dec. 2000.
[30] J. L. White, and A. A. Abidi, “Active resistor netwroks as 2-D sampled data filters,” IEEE J. Solid-State Circuits, vol. 39 no.9, pp.724-732, Sep. 1992.
[31] M. Choi and A. A. Abidi, “A 6 b 1.3 GSample/s A/D converter in 0.35 μm CMOS,” IEEE J. Solid-State Circuits, vol. 36, pp. 1847–1858, Dec. 2001.
[32] P. Scholtens and M. Verregt, “A 6-b 1.6-Gsample/s flash ADC in 0.18-μm CMOS using averaging termination,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp.
1599-1609, Dec. 2002.
[33] K. Sushihara, Kimura, Y. Okamoto, K. Nishimura, and A. Matsuzawa, “A 6 b 800 MSample/s CMOS A/D Converter,” IEEE Int. Solid-State Circuits Conf., pp.
428–429, Feb. 2000.
[34] G. Geelen, “A 6b 1.1Gsample/s CMOS A/D converter,” in ISSCC Dig. Tech.
Papers, Feb. 2001, pp. 128-129.
[35] S. Sheikhaei, S. Mirabbasi, and A. Ivanov, “A 0.18μm CMOS pipelined encoder for a 5 GS/s 4-bit flash analogue-to-digital converter,” Canadian Journal of.
[36] K. Uyttenhove, and M. S. J. Steyaert, “A 1.8-V 6-Bit 1.3-GHz Flash ADC in 0.25-μm CMOS,” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1115 - 1122, July 2003.
[37] C. Protmann and T. Meng, “Power-Efficient Metastability Error Reduction in CMOS Flash A/D Converters,” IEEE J. of Solid-State Circuits, vol. 31, no. 8, pp.
1132-1140, Aug. 1996.
[38] D. Seo, and G. H. McAllister, “A Low-Spurious Low-Power 12-bit 160-MS/s DAC in 90-nm CMOS for Baseband Wireless Transmitter,” IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 486 - 495, March 2007.
[39] Chen-Kang Ho, and Hao-Chiao Hong, “A 6-GS/s, 6-bit, at-speed testable ADC and DAC pair in 0.13µm CMOS,” VLSI Design, Automation and Test, pp.
207-210, April 2009.
[40] A. V. den Bosch, M. Steyaert, and W. Sansen, “SFDR-BANDWIDTH LIMITATIONS FOR HIGH SPEED HIGH RESOLUTION CURRENT STEERING CMOS D/A CONVERTERS,” in Proc. IEEE International Conference on Electronics, Circuits and Systems (ICECS), vol. 3, pp. 1193 - 1196, Sept. 1999.
[41] A. V. den Bosch, M. A. F. Borremans, M. S. J. Steyaert, and W. Sansen, “A 10-bit 1-GSample/s Nyquist Current-Steering CMOS D/A Converter,” IEEE J.
Solid-State Circuits, vol. 36, no. 3, pp. 315 - 324, March 2001.
[42] D. A. Mercer, “Low-Power Approaches to High-Speed Current-Steering Digital-to-Analog Converters in 0.18-μm CMOS,” IEEE J. Solid-State Circuits, vol. 42, no. 8, pp. 1688 - 1698, Aug. 2007.
[43] A. V. Oppenheim and R. W. Schafer, “Discrete-Time Signal Processing, 2nd Edition,” Prentice Hall, 1999.
[44] J Jacob Wikner, “STUDIES ON CMOS DIGITAL-TO-ANALOG CONVERTERS,” Linköping Studies in Science and Technology Dissertation No.
667.
[45] S. Seemi, Mohd-Shahiman Sulaiman, and A.S. Farooqui, “A 1.3-Gsample/s interpolation with flash CMOS ADC based on active interpolation technique,”
Journal of Analog Integrated Circuit and Signal Processing, vol. 47, No. 3, pp.
273-280, June 2006.
[46] B. Verbruggen, J. Craninckx, M. Kuijk, P. Wambacq, and G. Van der Plas, “A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm Digital CMOS,” in Proc. IEEE Int. Solid-State Circuits Conf. 2008, pp. 252–254.
[47] Ying-Zu Lin, Cheng-Wu Lin and Soon-Jyh Chang, "A 2-GS/s 6-bit Flash ADC with Offset Calibration," IEEE Asian Solid-State Circuits Conference, pp.385-388, 2008.
[48] Bo-Wei Chen, Szu-Kang Hsien, Cheng-Shiang Chiang and Kai-Cheung Juang, "
A 6-Bit, 1.2-GS/s ADC with Wideband THA in 0.13-μm CMOS," IEEE Asian Solid-State Circuits Conference, pp.381-384, 2008.
[49] Yuji Nakajima, Akemi Sakaguchi, Toshio Ohkido, Tetsuya Matsumoto, and Michio Yotsuyanagi, “A Self-Background Calibrated 6b 2.7GS/s ADC with Cascade-Calibrated Folding-Interpolating Architecture” in Symposium on VLSI Circuits Digest of Technical Papers, pp.266-267, June 2009.
[50] M. Choi, J. Lee, J. Lee, and H. Son, “A 6-bit 5-GSample/s Nyquist A/D converter in 65 nm CMOS,＂ in Symp. VLSI Circuits Dig. Tech. Papers, Jun.
2008, pp. 16–17.
[51] Kazuaki Deguchi, Naoko Suwa, Masao Ito, Toshio Kumamoto and Takahiro Miki,
"A 6-bit 3.5-GS/s 0.9-V 98-mW Flash ADC in 90nm CMOS", IEEE J. Solid-State Circuits, vol. 43, pp. 2303-2310, Oct. 2008.
[52] Aida Varzaghani, and Chih-Kong Ken Yang, “A 4.8 GS/s 5-bit ADC-Based Receiver With Embedded DFE for Signal Equalization,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 3, MARCH 2009.
[53] J. Jung, K. Baek, S. Lim, S. Kim, and S. Kang, "Design of a 6 bit 1.25 GS/s DAC for WPAN", in Proc. ISCAS, 2008, pp.2262-2265.
[54] P. Palmers, X. Wu, and M. Steyaert, “A 130 nm CMOS 6-bit full Nyquist 3 GS/s DAC,” in IEEE Asian Solid-State Circuits Conf., 2007, pp. 348–351.