The WKF, PVE, and RDF fluctuated Cg are presented in Figs. 5.4(a)- 5.4(c), where the solid line shows the nominal case with expected device dimensions, workfunction, and
5.2 : AC Characteristic Fluctuation 135
1.48×1018cm−3continuous channel doping. The different intrinsic parameter fluctuations induced rather different C-V characteristics. Figure 3(d) summarizes the gate capacitance fluctuations (σCg) with 0 V, 0.5 V and 1.0 V gate bias. Different to the results of Vth fluc-tuation, the WKF brought less impact on gate capacitance fluctuation. At low gate bias or negative gate bias, the accumulation layer screens the impact of WKF. Additionally, at low gate bias, the total capacitance decreases because of the increased depletion region. The associated value of Cg fluctuation is small. The capacitive response is then dominated by increment of inversion in the moderate inversion. The device characteristics are then im-pacted by intrinsic parameter fluctuated electrostatic potentials. If the high VGis achieved, the capacitive response becomes dominated by the inversion layer, the impact of the indi-vidual dopants on the device electrostatics is screened by the inversion layer itself. The variation of capacitance is now again becomes the variation of gate oxide. The impact of WKF induced electrostatic potential variations is therefore bringing less impact on channel surface. Our preliminary results show that the RDF and PVE dominate the gate capaci-tance fluctuations at all gate bias conditions, respectively. The impacts of the WKF on Cg
is reduced significantly at high gate voltage (VG) due to the screening effect of inversion layer of device, which screens the variation of surface electrostatic potential and decreases the fluctuation of gate capacitance. The screening effect resulting from the inversion layer also decreases the RDF induced gate capacitance fluctuation at high gate bias; however,
136 Chapter 5 : Intrinsic Parameter Fluctuation in Fin-Typed Field Effect Transistors
the screening effect of inversion layer is weakened by discrete dopants positioned near the channel surface. Notably, the PVE brings direct impact on gate length and therefore influ-ences the gate capacitance. The PVE induced gate capacitance fluctuation is independent of screening effect and should be noticed when the transistor operated in high gate bias, as shown in Fig. 5.4(d).
Attention should be drawn on the existence of nonlinear effect for gate capacitance fluctuation. Figure 5.5(a) plots the Cg-VG characteristics of 16 nm planar NMOSFETs with discrete dopant fluctuations. The solid and dot lines are the cases with and without random-dopant-position effect, respectively. The cases without random-dopant-position effect are simulated by changing their channel doping concentration continuously from 1.0×1015 cm−3 to 3.4×1018 cm−3. Figure 5.5(b) plots the slope of the Cg-VG curves, in which the gate capacitance is fixed to 5.0×10−18 F. The dash line indicates the cases without position effect, and the symbols are the cases with random-dopant-position effect. The slope of Cg-VG curve for the cases without random-dopant-position effect is nearly independent of doping concentration, which implies the lateral shift of the Cg-VG curves. The lateral shift of gate capacitance is resulted from the variation of Vth, and can be described by the correspond parameters in compact model. However, the slopes of Cg-VG curves are substantially altered as the random-dopant-position effect is taken into consideration, as shown in Fig. 5.5(b). The variation of the slopes of Cg-VG curves
5.2 : AC Characteristic Fluctuation 137
Figure 5.4: The Cg-VGcharacteristics for the explored devices with (a) PVE, (b) WKF, and (c) RDF. (d) The Cgfluctuation for 16-nm-gate MOSFETs with WKF, PVE, and RDF. The applied voltage for the bars are VG= 0, 0.5, and 1 V, respectively.
138 Chapter 5 : Intrinsic Parameter Fluctuation in Fin-Typed Field Effect Transistors
Figure 5.5: The (a) Cg-VGcurves and (b) the slope of the Cg-VGcurves for cases with and without taking random-dopant-position effect into consideration, where the solid line shows the nominal case and the dashed lines are
random-dopant-fluctuated devices. The solid and dot lines in (a) are the cases with and without
random-dopant-position effect, respectively. The dash line in (b) indicates the cases without random-dopant-position effect, and the symbols are the cases with
random-dopant-position effect. The (c) normalized gate capacitance fluctuation and (d) maximum gate capacitance fluctuation are calculated. (e) The C fluctuation with different drain bias.
5.2 : AC Characteristic Fluctuation 139
Figure 5.6: The Cgfluctuation for planar MOSFETs and SOI FinFETs with WKF, PVE, and RDF. The filled-in bars are the results of planar MOSFETs and the open bars are the results of SOI FinFETs.
indicates the change of shape of Cg-VG curves, as illustrated in Fig. 5.5(a). The variation of Cg-VGcurves is resulted from the randomness of dopant position in the depletion region of channel and therefore is hard to be described in current compact model [64-67,77]. To the best of the author’s knowledge, the fluctuation in gate capacitance has not yet been modeled and a coupled device-circuit simulation must be performed to estimate its impact on circuit characteristics. Figure 5.5(c) plots the normalized Cg fluctuation as a function of gate bias. The Cg fluctuations are normalized by the nominal Cg. The result implies the
140 Chapter 5 : Intrinsic Parameter Fluctuation in Fin-Typed Field Effect Transistors
importance of random-dopant- position effect. Moreover, the device under subthreshold operation suffers from the largest fluctuation. For device with high gate voltage (VG), the screening effect of inversion layer of device screens the variation of electrostatic potential and decreases the fluctuation of gate capacitance [77]. The normalized maximum variations of Cg are summarized in Fig. 5.5d), in which the normalized maximum variation of Cg is about 18.9%. The neglect of the random-dopant-position effect may under estimate the Cg
fluctuation by a factor of five. Figure 5.5(e) shows the σCg with different drain bias. The device with high drain bias has a less gate capacitance fluctuation due to the pinch-off effect and smaller gate-to-drain capacitance at a high drain bias. Figure 5.6 compares the gate capacitance fluctuations for planar MOSFETs and SOI FinFETs. Under the layout area, the SOI FinFETs exhibits a larger gate capacitance fluctuation due to the large numbers of dopants in the large depletion region of the SOI FinFETs.
Figures 5.7 and 5.8 show the cutoff frequency (FT = vsat / 2πLg = gm / 2πCg) and its fluctuation versus the gate voltage for planar MOSFETs and SOI FinFETs, in which the solid line shows the nominal case with 1.48×1018 cm−3 channel doping, the dashed lines are fluctuated cases, and the symbol line shows averaged result. The gm and vsat are the transconductance and the saturation velocity of the transistors, respectively. The planar MOSFETs possess higher FT than that of FinFETs due to the smaller gate capacitance;
WKF-induced FT fluctuation diminished as the saturation of the carrier velocity occurs.
5.2 : AC Characteristic Fluctuation 141
Figure 5.7: The (a)WKF, (b)PVE, and (c) RDF induced FT
characteristics fluctuation of planar MOSFETs. (d)The summarized FT fluctuations.
142 Chapter 5 : Intrinsic Parameter Fluctuation in Fin-Typed Field Effect Transistors
Figure 5.8: The (a)WKF, (b)PVE, and (c) RDF induced FT
characteristics fluctuation of FinFETs. (d)The summarized FT fluctuations.
5.3 : Summary 143
However, the PVE-induced FT fluctuation is still significant owing to the direct influence of gate length (Lg) on gate capacitance. As for RDF, the carrier-impurity scattering alters the saturation velocity, and therefore FT fluctuation does not diminish in high-field region.
It’s worth to note that the nominal and the averaged values of FT are similar to the results of WKF and PVE. However, in RDF, the deviation between the nominal and the averaged FT increases as VG increases due to the randomness of carrier-impurity scattering events and carrier velocity variations. As shown in Figs. 5.7(d) and 5.8(d), RDF plays the dominating factor in the FT fluctuation. For planar MOSFETs, PVE become dominates FT fluctuation as VGlarger than 0.6 V due to the screening effect in RDF and WKF fluctuations. The ob-tained results are similar to the results as shown in Fig. 5.4(d), in which the PVE dominates the gate capacitance fluctuation in high gate voltage. As for the SOI FinFETs, the RDF is the dominant fluctuation sources due to the larger gate area and smaller WKF and PVE fluctuation comparing to planar MOSFETs.
5.3 Summary
This chapter have estimated the influences of the intrinsic parameter fluctuations in 16-nm-gate devices. The dimensions of planar MOSFETs and SOI FinFETs are designed to have the same layout area; also, their threshold voltages were calibrated to 140 mV. The RDF dominates the Vth fluctuation of FinFETs in both NMOSFETs and PMOSFETs. However,
144 Chapter 5 : Intrinsic Parameter Fluctuation in Fin-Typed Field Effect Transistors
for planar transistors, the Vth fluctuation of PMOS is mainly determined by the WKF be-cause of the large deviation of the workfunction for different grain orientation. Although the WKF in SOI FinFETs is less important due to the large gate coverage area of the designed device structure, the impact of WKF starts to draw people’s attention device reli-ability. As for the AC characteristics, the nonlinear variation of Cg-VGcurves resulted from the randomness of dopant position in the depletion region of channel has been found. The nonlinear effect is hard to be described in current compact model, and therefore a coupled device-circuit simulation were employed to estimate its impact on circuit characteristics.
The impacts of the WKF on Cgis reduced significantly at high gate voltage (VG) due to the screening effect of inversion layer of device. The screening effect resulting from the inver-sion layer also decreases the RDF induced gate capacitance fluctuation at high gate bias;
however, it is weakened by discrete dopants positioned near the channel surface. Notably, the PVE induced gate capacitance fluctuation is independent of screening effect and should be noticed.
Chapter 6
Implication of Device Variability in Circuits
The impact of intrinsic parameter fluctuation on device reliability has been discovered in the previous chapter. This chapter then explores the associated device variability in the state-of-art circuits using nanoscale transistors. Since there is no well-established compact models for describing the behaviors of nanoscale transistors, the coupled device-circuit simulation approach [64-67,115-118] is then developed to ensure the best simulation ac-curacy. Then the implication of nanoscale device variability in circuits is studied and the dominant fluctuation sources in each circuit characteristics are identified and verified.
145
146 Chapter 6 : Implication of Device Variability in Circuits
6.1 The Coupled Device-Circuit Simulation Technique
For state-of-art nanoscale VLSI circuits and systems, the local device variation and un-certainty of signal propagation time have become crucial in the variation of system tim-ing and the high frequency characteristics. Yield analysis and optimization, which take into account the manufacturing tolerances, model uncertainties, variations in the process parameters, and other factors are known as indispensable components of the circuit de-sign procedure [44-48]. Diverse approaches have recently been presented to investigate fluctuation-related issues in transistors [21-27,62-83] and circuits [61-67,84-89]. However, most of they relies on the use of compact models. Thought the extraction of compact model provides an efficient way to estimate circuit characteristics fluctuation, the random dopant induced nonlinear device gate capacitance fluctuations make the device character-istics difficult to be modelled using present compact models [64-67,77]. Moreover, the well-established compact model of ultrasmall nanoscale devices is not available yet. To capture the discrete-dopant-position-induced fluctuations in nanoscale transistor circuits, a coupled device-circuit simulation approach [64-67,115-118] is then proposed. The char-acteristics of the devices of the circuit are first estimated by solving the device transport equations. The obtained result is then used as initial guesses in the coupled device-circuit simulation. The nodal equations of the test circuit are formulated and then directly coupled to the device transport equations (in the form of a large matrix that contains both circuit
6.1 : The Coupled Device-Circuit Simulation Technique 147
Figure 6.1: Time domain coupled device circuit simulation flow [64-67,115-118]. The characteristics of the devices of the circuit are first estimated by solving the device transport equations. The obtained result is then used as initial guesses in the coupled device-circuit simulation. The nodal
equations of the test circuit are formulated and then directly coupled to the device transport equations, which are solved simultaneously to obtain the devices and circuit
characteristics.
148 Chapter 6 : Implication of Device Variability in Circuits
Figure 6.2: The (a) inverter circuit and (b) common source amplifier circuits as examples for digital and analog/high-frequency characteristics fluctuation exploration.
and device equations), which are solved simultaneously to obtain the circuit characteristics.
The device characteristics, such as distributions of potential and current density, obtained by device simulation are input in the circuit simulation through device contacts. The effect of discrete dopants in the transistor on circuit characteristics is thus properly estimated.
The time domain coupled device-circuit simulation chart is shown in Fig. 6.1. Fig-ures 6.2(a) and 6.2(b) are the inverter circuit and common source amplifier circuits as examples for digital and analog/high-frequency characteristics fluctuation exploration. In
6.1 : The Coupled Device-Circuit Simulation Technique 149
coupled device-circuit simulation, the time dependent device transport equations are shown in below: The above equations represent the Poisson equation, current continuity equation for elec-tron, current continuity equation for hole, and quantum corrected equation for electron and hole. φ, n, p, t, and T are the electrostatic potential, electron densities, hole densities, time, and temperature to be solved, respectively. εs is the silicon permittivity, 1.05×10−10 F/m. q is the elementary charge, 1.06×10−19Coulombs. kBis Boltzmann constant, 8.6174
×10−15eV/K. R, µn, and µpare the net electron-hole recombination rate, electron and hole mobilities. ND and NA are the number of ionized donors and acceptors, respectively. γn and γp are the quantum potential for electrons and holes. bn and bp are density-gradient coefficient for electrons and holes. ~ is the reduced Planck constant. m∗nand m∗pare the ef-fective mass for the electrons and holes. The following equations express the circuit nodal
150 Chapter 6 : Implication of Device Variability in Circuits
equations (node 1 to node 2) for a inverter circuit, as shown in Fig. 6.2(a).
Node1 : V1= VG, (6.5)
Node2 : V2= VDD, (6.6)
Node3 : ID,PMOS= ID,NMOS, (6.7)
and
Node4 : V4= 0. (6.8)
After solving the device transport equation, the device and circuit equations are coupled and solved simultaneously to obtain circuit characteristics. The coupled device-circuit sim-ulation approach directly transfers the device characteristics to circuit and connecting the device physics with circuit characteristics. The following shows the nodal equations of Fig. 6.2(b).