angle will result in better subthreshold swing; in particular, for those silicon fins with higher fin height, which improve the short-channel effect remarkably. Similarly, we also find the evidence for the drain induced barrier lowering. Consequently, for the cases with a small fin angle, the device may not have an acceptable performance. In addition, for the bulk FinFET with a high fin height, the situation is getting worse simultaneously. The fin height and the fin angle are the two critical limiting factors when the dimension of the bulk FinFET is continuously scaled down. The critical angles for the case of SS < 75 mV/dec and DIBL
< 75 mV/V are then estimated. It’ found that the critical angles when fin height / top fin
width = 1.5, 2 and 2.5, and the critical angles are 71.9o, 79.3o, and 87.4o, respectively. For device with a large ratio between the fin height and the top fin width, the controllability of manufacturing the fin taper angle is exceptionally important and much more efforts on processing should be made. A nearly rectangular shaped fin is only crucial for the device with a higher fin height. The following discussion of characteristics of FinFETs is based on an assumption that FinFET has a fin aspect ratio equal to one.
2.4 Summary
Nanoscale bulk FinFETs demonstrate potential application for sub-32 nm CMOS devices era, such as SRAM fabrication. This chapter described the quantum-mechanical corrected
46 Chapter 2 : Device Model and Numerical Methods
transport equations and numerical methods in device simulation, in which the density gra-dient was coupled with the drift-diffusion model for including the quantum mechanical ef-fects. The coupled partial differential equations were approximated with the finite volume method over nonuniform mesh and then solved with the monotone iteration methods. The mobility model including bulk mobility, acoustic phonon scattering, and surface roughness scattering effects were calibrated and used for device simulation. Electrical characteristics of 25-nm-gate round-top-gate fin-typed field effect transistors (FinFETs) on silicon wafers are then calibrated with experimentally measured data and explored. Result shows that the importance of fin height and the fin angle in FinFETs scaling. To have a transistor with SS
< 75 mV/dec and DIBL < 75 mV/V, the critical angles for fin height / top fin width = 1.5, 2
and 2.5 are 71.9o, 79.3o, and 87.4o, respectively. Examinations into the effects of the top fin width and wider variation of ratio (e.g., ratio < 1) on electrical characteristics will benefit the device design. Characteristic fluctuation of bulk FinFETs should also be controlled for high performance design. The intrinsic parameter induced characteristics fluctuation for the nanoscale FinFETs are presented in following chapters.
Chapter 3
Simulation of Intrinsic Parameter Fluctuation
This chapter presents the characterization technique for intrinsic parameter fluctuations consisting of process-variation-effect (PVE), random-dopant-fluctuation (RDF), and an emerging fluctuation source: workfunction fluctuation (WKF). The characterization ap-proaches are examined with experiment data. Base upon the independent of random vari-ables, the total threshold voltage fluctuation, σVth,total, is expressed as follows [137]:
σ2Vth,total ≈ σ2Vth,RDF + σ2Vth,P V E+ σ2Vth,W KF, (3.1)
where σVth,RDF, σVth,P V E, and σVth,W KF are the threshold voltage fluctuations caused by the process-variation-effect, random-dopant-fluctuation, and the workfunction fluctuation,
47
48 Chapter 3 : Simulation of Intrinsic Parameter Fluctuation
respectively. The statistical addition of individual fluctuation sources herein, Equation (1), simplifies the variability analysis of nano-devices and circuits, significantly [137].
3.1 Process Variation Effect
Figure 3.1: (a) An illustrates for the result of generated profile. The process-variation-effect induce gate length variation,
σLg,P V E, are obtained. The inset shows the equation for the estimation of σVth,P V E. (b)A look-up table of the threshold voltage versus gate length. Using the Vth roll-off relation, the σVth,P V Ecan be obtained.
During the manufacturing process, the inevitable variations of processing condition
3.1 : Process Variation Effect 49
cause variations on device geometry, such as non-uniform gate oxide and material inter-face facial layer thickness, gate length deviation, line edge roughness, and so on [95]. All these fluctuations are getting worse with gate-length scaling. Among these process vari-ation induced fluctuvari-ations, the gate-length devivari-ation and the line edge roughness are the dominating factors; therefore, the fluctuations induced by these two effects are focused.
Line edge roughness is arising not only from the resolution limit of lithography but also from the grainy nature of photo resist and gate. The effect of line width roughness is random and cannot be corrected by optical proximity correction. Therefore, a statistical approach is applied herein to evaluate the effect of process-variation-induced σVth.
Figure 3.1(a) illustrates an example for the result of generated profile. The generation is similar to extraction of piecewise device gate length from SEM picture. The statistically generated profile is then averaged to obtain the effective gate length of a transistor. Then the process-variation-effect induce gate length variation, σLg,P V E, are obtained. The mag-nitude of the σLg,P V E follows the roadmap of ITRS that 3σLg = 0.9 nm and 3σLER = 1.2 nm for the 22 nm node and 3σLg = 0.7 nm and 3σLER = 0.8 nm for the 16 nm technol-ogy node, as the inset table of Fig. 3.1(b). Fig. 3.1(b) is a look-up table of the threshold voltage versus the gate length is established. It enables us to evaluate the threshold voltage with respect to the gate length variation. Since the ∆Lg and ∆Vth are known parame-ters for the roll-off characteristics, the σVth,P V E can be obtained for a given σLg,P V E,
50 Chapter 3 : Simulation of Intrinsic Parameter Fluctuation
σVth,P V E = σLg,P V E ×
³∆Vth
∆Lg
´
. Notably, σLg,P V E can be obtained from SEM critical dimension measurements.