Table 4.3: Summary of the threshold voltage fluctuation of the explored planar MOSFETs and bulk FinFETs.
Vth,total 61.2 49.5 39.8 31.0 30.7
4.2 Silicon-on-Insulator Transistors
This subsection initially discusses the physical fluctuations that are induced by discrete dopants, and then the characteristic fluctuations and mechanism of immunity against fluc-tuations of multiple-gate SOI devices are studied. The dopant generation and simulation has been presented in previous chapters. Figure 4.20 displays the explored 16-nm-gate single-, double-, triple- and surrounding-gate SOI devices. Discrete-dopant-induced fluc-tuations, caused by local potential spikes, are determined by the corresponding dopants within the device channel. The potential spike alters not only the electric field and current conducting path, but also the electron velocity, carrier mobility and electron temperature distribution.
Figure 4.21 depicts for example discrete-dopant-induced fluctuations of a triple-gate
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Chapter 4 : Random-Dopant-Induced Characteristics Fluctuation in Vertical-Channel Devices
Figure 4.20: The (a) single-gate; (b) double-gate; (c) triple-gate; and (d) quadruple surrounding-gate for the dopant
position/number-sensitive device simulation.
SOI transistor. All cross-sectional plots of the distributions of the on-state current den-sity and the contours of the off-state potential are extracted 1nm below the top-gate oxide.
Figures 41(a) and 4.21(a’) refer to the nominal case (continuous doping is assumed) and the discretely doped case, respectively. The on-state potential contour and current density distribution of the discretely doped case, shown in Figs. 4.21(b’), and 4.21(c’), are inves-tigated to elucidate the effect of discrete dopant on the potential and current distribution of the device. The potential spikes in Fig. 4.21(b’) are associated with the corresponding
4.2 : Silicon-on-Insulator Transistors 107
Figure 4.21: Comparison of the on-state potential contours ((b) and (b’)), the current density distributions ((c) and (c’)), the electric field ((d) and (d’)), the electron velocity ((e) and (e’)), and the electron temperature ((f) and (f’)) of the (a) the nominal case and (a’) discretely doped cases. The potential spikes (marked as A, B, and C) in (b’) are induced by corresponding dopants in (a’)). All cross-sectional plots of the on-state current density distributions and off-state potential contours are extracted at 1 nm below the top-gate oxide.
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Chapter 4 : Random-Dopant-Induced Characteristics Fluctuation in Vertical-Channel Devices dopants (spikes A, B and C) in Fig. 4.21(a’). The potential distribution near spike C does not vary significantly with structure of the triple-gate. Comparison of Figs. 4.21(c) and 4.21(c’) reveals that the current conducting path is disturbed and impeded by dopants in the channel. Changing the number and position of discrete dopants in the channel causes a significant potential variation and change in current. The current may avoid the high potential barrier region and pass through the valley between two potential spikes (such as spikes A and B). Additionally, the local field distribution, shown in Fig. 4.21(d’), is also perturbed significantly by discrete dopants. In the on-state condition (the gate voltage VG= 1V; the drain voltage VD= 1V), since the potential distribution near the dopant is relatively negative in the channel, the dopant acts as a center of a whirlpool-like electric field to re-pel electrons. As electrons drift from source to drain, some of them encounter a negative electric field that is induced by the dopant. The lateral electric field between the source and the drain, combined with the repulsion of the dopants, twists the electron field and increases the electron velocity near the dopant, as shown in Figs. 4.21(e), and 4.21(e’).
This phenomenon explains why the distribution of the electron velocity remains the same to the left of the dopants at device’s source. The fluctuation in the electron velocity also in-dicates a fluctuation of the distribution of electron temperatures, as plotted in Figs. 4.21(f) and 4.21(f’).
4.2 : Silicon-on-Insulator Transistors 109
Figure 4.22: The ID-VG characteristics of the 500
discrete-dopant-fluctuated 16-nm-gate single- and multiple-gate SOI devices, where the solid lines indicate the nominal case and the dash lines indicate the discretely doped cases.
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Chapter 4 : Random-Dopant-Induced Characteristics Fluctuation in Vertical-Channel Devices
Figure 4.23: The on-off state current characteristics of the 500 discrete-dopant-fluctuated 16-nm-gate single- and multiple-gate SOI devices. (a) Comparison between the single- and double-gate devices. (b) Comparison among the double-, triple-, and quadruple surrounding-gate devices.
4.2 : Silicon-on-Insulator Transistors 111
Figure 4.24: (a) Comparison of Vthfluctuation of the 16-nm-gate single- and multiple-gate SOI MOSFETs. (b) Plots of the standard deviation (S.D.) and the maximum difference of Vthwith respect to different gate number.
112
Chapter 4 : Random-Dopant-Induced Characteristics Fluctuation in Vertical-Channel Devices The characteristic fluctuations of multiple-gate SOI devices are also investigated. Fig-ure 4.22 plots fluctuations of ID-VG for single- and multiple-gate SOI devices. The solid lines represent the nominal case and the dashed lines represent the discretely doped cases.
The spread of the ID-VG curves shows the magnitude of the current fluctuation that is in-duced by discrete dopants. The result shows that the single-gate device exhibits much larger current fluctuations than the multiple-gate devices. Figure 4.23 plots the correspond-ing on- and off-state current characteristics. For cases with similar on-state currents, the maximum fluctuation of the off-state current declines as the number of gates increases;
moreover, the maximum fluctuation of Iof f in multiple-gate devices is within 20 nA/um, whereas the planar device (with a single gate) exhibits a much larger fluctuation of Iof f (>
2000 nA/um). Figure 4.24(a) statistically compares the threshold voltage fluctuations of the aforementioned devices. As expected, the multiple-gate device exhibits better immu-nity against fluctuation and the magnitude of the Vth fluctuation (both standard deviation and difference between maximum and minimum Vth declines as the number of gates in-creases, as plotted in Fig. 4.24(b). The standard deviations (S.D.) of single-, double-, triple- and surrounding-gate devices are 102 mV, 46.2 mV, 30.9 mV and 25.5 mV, respec-tively. Calculations demonstrate that the fluctuations of Vth of the double-, triple- and quadruple surrounding-gate devices are 2.2, 3.3 and four times smaller, respectively, than that of the planar SOI device. The equivalent channel doping concentration increases with
4.2 : Silicon-on-Insulator Transistors 113
the dopant number, substantially altering Vth, as shown in Fig. 4.24(a), and the on- and off-state currents, as plotted in Fig. 4.22. The magnitude of spread increases with the number of dopants increases. The discrete-dopant-position affects the fluctuation of characteristics in a different manner for a fixed number of dopants.
The mechanism of immunity of single- and multiple-gate devices against fluctuation is studied with reference the extracted physical quantities. Figures 4.25(b) - 4.25(e) plot the on-state potential along the center of the device’s channel, shown in Fig. 4.25(a), and display 3D electric fields of single-, double-, triple- and quadruple surrounding-gate devices, respectively. The potential and electric field of multiple-gate devices are more uniform than those of the planar device because the channel controllability is better than that of a planar device for a large gate-coverage ratio. Figure 4.26 compares the on-state current density, plotted in Figs. 4.26(a) - 4.26(d), and the contour of the off-state potential, shown in Figs. 4.26(a’) - 4.26(d’), for the 16-nm-gate single-, double-, triple- and quadru-ple surrounding-gate SOI devices, respectively. All cross-sectional plots of the on-state current density and the off-state potential are at 1 nm below the top-gate oxide. As the gate-coverage ratio is increased, the on-state current density is increased and the heights of off-state potential spikes (A, B and C in Fig. 4.26(a)) are reduced. The lateral-gate struc-ture of triple- and quadruple surrounding-gate devices effectively suppresses the potential (spike C), and then increases the on-state current at the lower side of the channel, shown
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Chapter 4 : Random-Dopant-Induced Characteristics Fluctuation in Vertical-Channel Devices
Figure 4.25: Plots of the on-state potential and 3D electric field
distribution of the 16-nm-gate SOI MOSFET with the (b) single- (c) double-, (d) triple- and (e) quadruple
surrounding-gate structure. The cross-sectional plots of the on-state potential distributions are extracted along the center of the device’s channel, as shown in (a).
4.2 : Silicon-on-Insulator Transistors 115
Figure 4.26: Plots of the on-state current density distributions ((a)-(d)) and the off-state potential contours ((a’)-(d’)) of the 16-nm-gate SOI MOSFETs ((a) and (a’) are for the single-gate; double-gate: (b) and (b’); triple-gate: (c) and (c’); quadruple surrounding-gate: (d) and (d’)). The potential spikes in (a’)-(d’) are induced by corresponding dopants in channel (spikes A, B, and C shown in (a)). The height of potential spikes is decreased as gate number is increased. All cross-sectional plots of the on-state current density distributions and off-state potential contours are extracted at 1 nm below the top-gate oxide.
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Chapter 4 : Random-Dopant-Induced Characteristics Fluctuation in Vertical-Channel Devices
Figure 4.27: Plots of the lateral-side ((a)-(d)) and bottom-gate ((a’)-(d’)) on-state current density distributions of the 16-nm-gate devices ((a) single-gate; (b) double-gate; (c) triple-gate; (d) quadruple surrounding-gate). All
cross-sectional figures are extracted at 1 nm below the lateral-side and bottom-gate oxides.
4.2 : Silicon-on-Insulator Transistors 117
in Figs. 4.26(c) and 4.26(d). The lateral-gate of multiple-gate intrinsically enhances the controllability of dopant-induced fluctuations near the sidewall of the channel surface. It also accounts for why spike ”C” in Fig. 4.21(a’) has a weaker influence on the potential distribution than spike ”B”. Figure 4.27 shows the lateral- and bottom-gate on-state current densities of the structures. Similarly, all cross-sectional plots are obtained at 1 nm below the lateral- and bottom-gate oxides. Once current paths are impeded by discrete dopants on parts of channel surface, the well-gate-controlled multiple-gate structure bridges alternative conducting paths to prevent a significant fluctuation of the conduction current. Thus, the benefit of the superior vertical channel structure is that multiple-gate devices suppress po-tential fluctuation and provide a more stable conduction current than the planar device. As a result, the immunity against fluctuation in multiple-gate SOI devices results mainly from the uniform potential distribution and the fact that the current conduction area (multiple paths) is larger than that of a planar SOI device.
Besides the aforementioned multiple-gate devices, nanowire FinFETs are ultimate struc-tures and potential candidates for next generation nanoelectronic devices [16-18, 29-39].
Due to the limitation of manufacturability, nanowire transistors with a perfect gate struc-ture (i.e., a surrounding gate with 100% gate-coverage ratio) theoretically are not always guaranteed. Impact of the discrete dopants on device performance is crucial in determining the behaviour of nanoscale semiconductor devices. The immunity of nanowire transistor
118
Chapter 4 : Random-Dopant-Induced Characteristics Fluctuation in Vertical-Channel Devices against random discrete-dopant-induced fluctuation may suffer from the variation of gate-coverage-ratio. This section first discusses the fluctuations of potential and current density due to discrete dopants; and then the impact of non-ideal nanowire gate-coverage ratio on immunity against discrete-dopant-induced fluctuations is studied.
Figure 4.28: The 16-nm-gate silicon nanowire transistor with structures of (a) surrounding-gate (i.e., 100% coverage), (b) the omega-gate with 80% coverage-ratio, and (c) the omega-gate with 70% coverage-ratio.
Figures 4.28(a) - 4.28(c) illustrates the 16-nm-gate silicon nanowire transistor with
4.2 : Silicon-on-Insulator Transistors 119
Figure 4.29: Comparison of the on-state potential ((a) and (b)), the current density distributions ((e) and (f)) of the (c) the nominal case and (d) discretely doped cases. The potential fluctuations are induced by corresponding dopants in (d)).
120
Chapter 4 : Random-Dopant-Induced Characteristics Fluctuation in Vertical-Channel Devices structures of surrounding-gate (i.e., 100% coverage), the omega-gate with 80% coverage-ratio, and the omega-gate with 70% coverage-coverage-ratio, respectively. The used physical models have been calibrated with experimental data. The on-state (the device is with VD = VG = 1V) potential distribution of the discretely doped case, shown in Figs. 4.29(a), and 4.29(b), are investigated to elucidate the effect of discrete dopant on the potential and current dis-tributions of the device. The potential fluctuations, shown in Fig. 4.29(b), are associated with the corresponding dopants in Fig. 4.29(d). Comparison between Figs. 4.29(e) and 4.29(f) reveals that the current conducting path is disturbed and impeded by the discrete dopants locating at the channel. Since the potential distribution near the dopant is rela-tively negative in the channel, the dopant acts as a center of a whirlpool-like electric field to repel electrons. As electrons transport from the end of source to the drain side, some of them will encounter a negative electric field that is induced by the discrete dopants. The lateral electric field between the source and the drain, combined with the repulsion of the dopants, twists the electric field and increases the electron velocity near the dopants. The potential fluctuations not only alter the electric field and current conducting path, but also the electron velocity, and carrier mobility.
Figure 4.30 shows the comparisons of potential and current density distributions, re-spectively, for the nanowire transistors with the surrounding-gate (i.e., 100% gate-coverage-ratio) and the omega-gate (i.e., 80% and 70% gate-coverage-ratios) structures. The discrete
4.2 : Silicon-on-Insulator Transistors 121
Figure 4.30: Comparison of potential (plots of (a’), (b’), and (c’)) and current density distribution (plots of (a”), (b”), and (c”)) in nanowire transistors with surrounding-gate (100%
gate-coverage-ratio) and omega-gate (80% and 70%
gate-coverage-ratio) structures.
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Chapter 4 : Random-Dopant-Induced Characteristics Fluctuation in Vertical-Channel Devices
Figure 4.31: Comparison of the threshold voltage fluctuation of the 16-nm-gate silicon nanowire FET with surrounding-gate, omega-gate with 80%, and 70% gate-coverage-ratio.
dopants positioned in the channel induce a potential fluctuation and substantially disturbs the current density distribution and the corresponding conduction path. The magnitude of potential and current density fluctuations is increased as the gate-coverage-ratio decreases.
The non-ideal gate-coverage disturbs the channel controllability of the explored nanowire transistors and thus decreases the immunity against discrete dopant induced fluctuation. In our study, for a 16-nm-gate silicon nanowire transistor, the threshold voltage fluctuations of the omega-gate devices with 80% and 70% gate-coverage are 1.04 and 1.19 times larger than that of the surrounding-gate structure, as shown in Fig. 4.31. For current fluctuations,
4.2 : Silicon-on-Insulator Transistors 123
Figure 4.32: Comparison of the on-off state current fluctuation of the 16-nm-gate silicon nanowire FET with surrounding-gate, omega-gate with 80%, and 70% gate-coverage-ratio.
the ratio is 1.75 and 4.5 times larger than that of the surrounding-gate one, as shown in Fig. 4.32. The results confirm that the influence of non-ideal gate-coverage on the distur-bances of the channel controllability of nanowire transistors. The immunity against discrete dopant induced fluctuation is thus decreased. Figure 4.33 shows the characteristics of the on-state and off-state currents (Ion-Iof f). For those cases with similar Ion, the maximum fluctuation of Iof f is within 0.05 nA/um. This figure discloses three different discrete-dopant channels, having similar values of Ion or Iof f but with various dopant positions.
The cross-sectional on-state current density and off-state potential distributions extracting
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Chapter 4 : Random-Dopant-Induced Characteristics Fluctuation in Vertical-Channel Devices
Figure 4.33: Effect of discrete-dopant-position in silicon nanowire FET, where the devices are with different Ionbut similar Iof f
4.2 : Silicon-on-Insulator Transistors 125
Figure 4.34: Effect of discrete-dopant-position in silicon nanowire FET, where the devices are with similar Ionbut different Iof f
126
Chapter 4 : Random-Dopant-Induced Characteristics Fluctuation in Vertical-Channel Devices from the center of channel are examined. Due to the difference of discrete dopant posi-tion, the different conduction paths of devices result in different on-state currents even we have very similar off-state currents, shown in Fig. 4.33. For the device having very similar on-state current with different off-state situations, Fig. 4.34 shows the off-state potential distribution at device’s channel. However, due to the effect of discrete dopant position, there is no potential barrier located in the channel region.
4.3 Summary
The dependence of the threshold voltage fluctuation of bulk FinFETs on device dimension was empirically fitted as σVth ∝ (W L)−0.25, which is superior to that of planar MOSFETs.
The preliminary results indicate the bulk FinFETs can not only provide better immunity against discrete-dopant-fluctuation induced threshold voltage fluctuations, but also show less sensitivity to device size than planar MOSFETs. The superior immunity against fluctu-ation and the more stable fluctufluctu-ation of threshold voltage roll-off indicate the bulk FinFET to be a promising device for the sub-16-nm era. For the SOI transistors, the fluctuations of Vth of double-, triple-, and quadruple surrounding-gate SOI MOSFETs and the influence of non-ideal gate coverage disturbs the channel controllability of nanowire FinFETs are shown. Thus, the benefit of the superior vertical channel structure is that multiple-gate de-vices suppress potential fluctuation and provide a more stable conduction current than the
4.3 : Summary 127
planar device. As a result, the immunity against fluctuation in vertical-channel devices re-sults mainly from the uniform potential distribution and the fact that the current conduction area (multiple paths) is larger than that of a planar transistors.
Chapter 5
Intrinsic Parameter Fluctuation in Fin-Typed Field Effect Transistors
Metal gate and multi-gate transistors are key technologies for the reduction of intrinsic pa-rameter fluctuations. However, the use of metal as a gate material introduces a new source of random variation due to the dependency of workfunction on the orientation of metal grains. The WKF-induced threshold voltage fluctuation has been reported and the scope is limited to the transistors [121,122]. Additionally, the device and circuit performance may depend on different device characteristics. The comprehensive understanding of the domi-nant fluctuation source in the device and circuit characteristic fluctuations is urgent for the development of nanoscale systems. Therefore, this chapter estimates the influences of the
128
5.1 : DC Characteristic Fluctuation 129
intrinsic parameter fluctuations consisting of metal gate workfunction fluctuation, process variation effect and random dopant fluctuation on 16-nm-gate planar MOSFET and SOI FinFET devices. The DC characteristics are examined in terms of I-V and Vth. The AC parameters are investigated in terms of gate capacitance (Cg) and cutoff frequency (FT).
Then the dominant fluctuation sources in different devices are found.
5.1 DC Characteristic Fluctuation
The devices we investigated are the 16-nm-gate bulk MOSFETs (width: 16 nm) and SOI FinFETs (fin width/fin height: 16 nm / 32 nm) with amorphous-based TiN/HfSiON gate stacks with an EOT of 1.2 nm [121]. The dimensions of planar MOSFETs and SOI FinFETs are designed to have the same layout area. To compare the MOSFETs and FinFETs on the same basis, their nominal channel doping concentrations are 1.48×1018cm−3 and the Vth are calibrated. Additionally, to compare fairly the NMOSFET- and PMOSFET-induced characteristic fluctuation and eliminate the effect of transistor size on fluctuation, the di-mensions of the PMOSFETs were the same as those of the NMOSFETs. For σVth,RDF of FinFETs, to consider the random fluctuation effect of the number and location of discrete channel dopants, 1516 dopants are randomly generated in a large cube, in which the equiv-alent doping concentration is 1.48×1018cm−3, as shown in Fig. 5.1(a). The large cube is then partitioned into 125 sub-cubes. The number of dopants may vary from two to 22, and
130 Chapter 5 : Intrinsic Parameter Fluctuation in Fin-Typed Field Effect Transistors
Figure 5.1: (a) An illustration of FinFET structure. 1516 dopants are randomly generated in a large cube of 80×80×160 nm3, in which the equivalent doping concentration is 1.48×1018 cm−3. The large cube is then partitioned into 125 sub-cubes of 16×16×32 nm3. The number of dopants in sub-cube may vary from two to 22, and the average number is 13 ((b)-(d)). These 125 sub-cubes are equivalently mapped into the device channel of device for the 3D device simulation with discrete dopants. (e) The Vthroll-off is used for PVE estimation. The PVE includes the gate length deviation and the line edge roughness, whose magnitude follow the projections of the ITRS roadmap [1]. (f) The σVth,W KF is estimated by a statistically sound Monte-Carlo approach.
Figure 5.1: (a) An illustration of FinFET structure. 1516 dopants are randomly generated in a large cube of 80×80×160 nm3, in which the equivalent doping concentration is 1.48×1018 cm−3. The large cube is then partitioned into 125 sub-cubes of 16×16×32 nm3. The number of dopants in sub-cube may vary from two to 22, and the average number is 13 ((b)-(d)). These 125 sub-cubes are equivalently mapped into the device channel of device for the 3D device simulation with discrete dopants. (e) The Vthroll-off is used for PVE estimation. The PVE includes the gate length deviation and the line edge roughness, whose magnitude follow the projections of the ITRS roadmap [1]. (f) The σVth,W KF is estimated by a statistically sound Monte-Carlo approach.