and
Node5 : V5= 0. (6.13)
The coupled device-circuit simulation is beneficial in studying of nanoscale transistor cir-cuits. Moreover, the simulation results may be further used for the construction reliable compact model including variability issues. Since the physical and mathematic accuracy of large-scale statistical methodology are verified, it’s believed the given simulation ap-proach can use for devices and circuits characterization and optimization.
6.2 Digital Circuits
The inverter circuit with planar MOSFETs circuit is first explored to illustrate the details of random-dopant-fluctuation in high-frequency integrated circuits. Then the comparison between FinFETs and planar devices circuit performance is drawn. Figure 6.3(a) shows the voltage transfer curves for the 16-nm-gate planar CMOS inverters with discrete dopants.
Two points on the voltage transfer curve determine the noise margins of the inverter. These are the maximum permitted logic ”0” at the input, VIL, and the minimum permitted logic
”1” at the input, VIH. The two points on the voltage transfer curve are defined as those values of Vin where the incremental gain is unity; the slope is -1 V/V. The nominal value and fluctuations of the VIL and VIH are shown in the insets of Fig. 6.3(a). σVIL exceeds
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Figure 6.3: (a) The voltage transfer curves for the studied 16-nm-gate planar MOSFET circuit. (b) The noise margins, NMLand NMH, as a function of the dopant number in the
NMOSFET and PMOSFET.
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σVIH because the σVth of NMOSFETs exceeds that of PMOSFETs. The maximum slope of the voltage transfer curve indicates the maximum voltage gain of the inverter. The 7% of normalized voltage gain fluctuation of the inverter is therefore estimated, as shown in the inset of Fig. 6.3(a). Figure 6.3(b) plots the noise margins for the logic ”0” and ”1”, NMH and NML, as a function of the dopant number. The NMH and NMLare defined in insets.
The NML is increased with the increasing dopant number in the NMOSFET due to the increased Vthof device. For the NMH, as numbers of dopant in the PMOSFET increases, the increased Vthof device may decrease the VIHof voltage transfer curve and thus increase the NMH. We notice that even for cases with the same number of dopants within device channel, their noise margins are still quite different due to the different distribution of random dopants. The noise margins of the inverter circuit increases as dopant number increases; however, the fluctuations of the noise margins are also increased due to the more sources of fluctuation in device channel region.
Figure 6.4(a) presents the input and output signals; the solid line represents the nom-inal case (continuously doped channel with a channel doping concentration of 1.48×1018 cm−3) and the dashed lines represent cases with discrete dopant fluctuations. The rise time (tr), fall time (tf), and hold time of the input signal are 2 ps, 2 ps, and 30 ps, respectively.
Figures 6.4(b) and 6.4(c) display the zoom-in plots of the falling and rising transitions.
The term tris the time required for the output voltage (Vout) to rise from 10% of the logic
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Figure 6.4: (a) The input and output signals for the
discrete-dopant-fluctuated 16-nm-gate planar inverter circuit. The magnified plots show (b) the fall and (c) the rise transitions, where the rise time, fall time, high-to-low delay time, and low-to-high delay time are defined.
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Figure 6.5: The fluctuations of (a) fall and (b) rise signal transition points as a function of dopant number in n-type and p-type MOSFETs for the discrete dopant fluctuated inverter circuits.
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Figure 6.6: The fluctuations of (a) high-to-low and (b) low-to-high delay time as a function of dopant number in n-type and p-type MOSFETs for the discrete dopant fluctuated inverter circuits.
6.2 : Digital Circuits 157
”1” level to 90% of the logic ”1”, and the tf denotes the time required for the output volt-age to fall from 90% of the logic ”1” level to 10% of the logic ”1” level. The low-to-high delay time and high-to-low delay time are defined as the difference between the times of the 50% points of the input and output signals during the rising and falling of the output signal, respectively. For the high-to-low transition, the NMOSFET is on and starts to dis-charge load capacitance, causing the output signal to transit from logic ”1” to logic ”0”.
Similarly, for the low-to-high transition characteristics, the PMOSFET is turned on and starts to charge the load capacitance, causing the output voltage to transit from logic ”0”
to logic ”1”. The 90% (t90%) and 10% (t10%) of the logic ”1” level are defined as start-ing points for the high-to-low and low to-high transition and plotted in Figs. 6.5(a) and 6.5(b), respectively. During the high-to-low signal transition, the output signal falls as the NMOSFETs is turned on. Therefore, the fluctuation of the starting points for high-to-low signal transition is determined by the Vth of the NMOSFET. With the increasing number of dopants in NMOSFET, the increased Vth delays the starting point of signal transition (t90%) and increases the high-to-low delay time, as shown in Fig. 6.6(a). Similarly, the starting point of low to-high transition (the time of 10% of the logic ”1” level) is influ-enced by Vth of PMOSFET and increased as numbers of dopants in PMOSFET, as shown in Fig. 6.5(b). Figures 6.6(a) and 6.6(b) plot the high-to-low delay time and low-to-high delay time for the planar inverter circuits with discrete dopants, respectively. Since the
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Table 6.1: Transition time variation for the 16-nm-gate planar inverter circuits. (* normalized by the nominal value)
(unit: ps) tr tf tLH tHL
Nominal 1.021 0.897 0.800 0.590
Fluctuation 0.036 0.021 0.105 0.108
Normalized Fluctuation* 3.5% 2.4% 13.2% 18.3%
Normalized Maximum Fluctuation* 23.2% 12.3% 73.5% 101.8%
delay time is dependent on the start of the signal transition, the tHL and tLH are increased as channel dopant number increases. Notably, even with the same dopant number inside the channel, the delay time can still vary significantly. Take the cases of six dopants inside the NMOSFETs as an example; the maximum tHL difference is about 0.3 ps, where the nominal tHL is 0.59 ps. We refer to this effect as discrete-dopant-position-induced fluctu-ation. The magnitude of discrete-dopant-position-induced fluctuations increases as dopant number increases because of the increasing number of fluctuation sources (dopants).
Table 6.1 summarized the normalized timing characteristic fluctuations (the standard deviation / nominal value × 100%). For the 16-nm-gate CMOS inverter, as the number of discrete dopants varies from zero to 14, fluctuations of tr, tf, tLH, and tHL, of 0.036, 0.021, 0.105, and 0.108 ps respectively, may occur. The normalized fluctuation for tr, tf, tLH, and tHLare 3.5%, 2.4%, 13.2%, and 18.3%, respectively. The delay time fluctuations dominate the timing characteristics. The normalized maximum fluctuations (the maximum
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Figure 6.7: The fluctuations of (a) the fall and (b) rise time as a function of the threshold voltage in the n-type and p-type MOSFETs for the discrete-dopant-fluctuated CMOS inverters.
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variation of time / nominal value × 100%) of the low-to-high and high-to-low delay times are about 73.5% and 101.8%. Notably, the maximum and minimum delays associated with this specific set of 125 randomized channels would vary such that their range would increase, as the number of samples increased. For the high-to-low signal transition of the output signal, the delay time is dominated by the starting points of the signal transition and then controlled by the on/off state of the NMOSFETs in the inverter planar circuit.
Therefore, the fluctuation of the threshold voltage of NMOSFETs substantially affects the high-to-low delay time characteristic. Similarly, the low-to-high delay time fluctuation is strongly influenced by the σVth of PMOSFETs. σtHL exceeds σtLH because the σVth of NMOSFETs exceeds that of PMOSFETs. The rise/fall time fluctuations depend on the charge/discharge capability of the PMOSFETs/ NMOSFETs. Therefore, σtr exceeds the σtf because the driving capability of PMOSFETs is weaker than that of NMOSFETs in the given device dimensions scenario. The device with larger driving capability requires less time to charge and discharge a given load capacitance and so exhibits a less fall time fluctuations. Figures 6.7(a) and 6.7(b) show the fall time and rise time as a function of the threshold voltage for NMOSFETs and PMOSFETs, respectively. The fall time is dependent on the discharge capability of the NMOSFETs, and the rise time is dependent on the charge capability of the PMOSFETs. As the threshold voltages of the NMOSFETs and PMOSFETs are increased, the discharge and charge ability for given values of tf and
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tr decrease. Therefore, the time required for the fall and rise transitions increases. The trend for tf is not clear because herein only the transistors gate capacitance was used as the load capacitance. The small load capacitance and strong driving capability of NMOSFETs make the trend of tf fluctuation insignificant. Notably, the rise and fall time fluctuations generally may not be as important as the delay time fluctuation in circuit timing; however, their maximum variations can exceed 0.237 and 0.110 ps, respectively, which exceed the delay time fluctuation and should therefore be considered in statistical timing analysis in circuit and system design. Moreover, fluctuations in the rise and fall time can be added to the delay time, and increasing the delay time fluctuations.
Figure 6.8(a) and 6.8(b) compare the high-to-low delay time (tHL) and low-to-high delay time (tLH) for the planar MOSFETs and FinFET devices. Since the tHLand tLH are dependent on the Vthfluctuations for NMOSFET and PMOSFET, respectively, according to the results of Fig. 5.3, the RDF and WKF are the dominating factors in timing fluctuations and WKF introduces a largest tLH fluctuation due to the large workfunction deviation in scaled gate area as shown in Fig. 5.3(b). The WKF has shown its increasing importance in nanoscale transistor, especially in PMOSFET characteristics. Figure 6.9 estimates the power for the studied transistors. The total power (Ptotal) is consisting of the dynamic power (Pdyn), the short circuit power (Psc), the static power (Pstat). Their definitions are
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Figure 6.8: Comparison of the variations of (a) tHLand (b) tLH with respect to WKF, PVE, and RDF for the planar MOSFETs and FinFETs.
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Figure 6.9: The nominal power for the bulk planar MOSFET and SOI FinFET inverter circuits.
shown in below.
Pdyn = CloadVdd2f0−>1 (6.14)
Psc = f0−>1VDD Z
T
Isc(τ )dτ (6.15)
, and
Pstat = VDDIleakage (6.16)
The f0−>1 is the clock rate. Isc is the short circuit current, which is observed as both NMOSFET and PMOSFET turned on resulting a DC path between the power rails. T is