In this section, electrical characteristics of 25-nm-gate round-top-gate fin-typed field ef-fect transistors (FinFETs) on silicon wafers are calibrated and explored. Furthermore, by considering different short-channel effects, dependence of the device performance on the non-ideal fin angle and fin height is investigated. Optimal structure configuration for the round-top-gate bulk FinFETs is thus drawn to show the strategy of fabrication in sub-25 nm metal oxide semiconductor field effect transistors devices. The physical models have been calibrated with experimentally measured data.
Field effect transistors with multiple-gate structures, such as fin-type FETs (FinFETs) have been of great interest due to the excellent controlling ability of carriers in the de-vice’s channel, which suppressed the short-channel effect. Channel doping for adjusting
2.3 : A 25-nm FinFET Simulation and Calibration 31
Figure 2.3: (a) An illustration of the simulated fin-type field effect transistors. The top of the fin is formed to a round shape naturally and the fin bottom is not actually rectangular for the lithography and silicon etching processes. (b) The ID-VGcurves for the FinFETs. The red and black lines are the simulated and measured data, respectively.
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Figure 2.4: SEM pictures of bulk FinFETs with a round-top and slant fin.
the threshold voltage is still necessary in nowadays manufacturing process. Various stud-ies have been reported to simulate the multiple-gate device by using 3D quantum/classical models, and device models coupled with process models. We herein use the 3D quantum-corrected drift-diffusion models to simulated the characteristics of bulk FinFETs. The em-ployed device models have been calibrated. Figure 2.3(a) shows the geometry and parame-ters of the simulated FinFET with 4.71 eV workfunction, 37.5 nm fin height (Hf in), 25 nm fin width (Wf in), 25 nm gate length (Lg) and 1.6 nm oxide thickness. The device is with a round-shape top due to the limit of manufacturing ability. In fabricating the nanoscale
2.3 : A 25-nm FinFET Simulation and Calibration 33
Figure 2.5: (a) The device dimension and parameter setting of the simulated fin-type field effect transistors, in which the device workfunction is 4.28 eV. (b) The characteristics of the ID-VGcurves for the FinFETs. The red and black lines are the simulated and measured data, respectively. The simulation shows a good agreement with measurement data, which represents the accuracy of the calibrated 3D device simulation.
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FinFETs, the minimum dimension of the device has transferred from the gate length to the fin thickness. Top of the fin is formed to a round shape naturally and the fin bottom is not actually rectangular for the lithography and silicon etching processes, as shown in Fig. 2.4.
These non-ideal processes will result in a wider fin bottom with respect to the fin top; thus it leads to a slanted edge of the channel fin [51-56]. Such geometric derivation degrades device performance and raises serious SCEs, such as a large subthreshold swing, low ratio of the on- and off-state currents, and large drain induced barrier lowering. The measure-ment and simulated results are presented in Fig. 2.3(b), where the red and black lines are the simulated and measured data, respectively. The simulation shows a good agreement with measurement data. Similarly, we change the device workfunction and parameters as shown in Fig. 2.5(a). The simulated data in Fig. 2.5(b) also exhibit a good accuracy with measurement data, which represents the accuracy of the calibrated 3D device simulation.
The properties of the material are summarized in Tab. 2.1.
Then we change the device geometry setting to explore the electrical characteristics of 25-nm-gate round-top-gate FinFETs on silicon wafers, as shown in Fig. 2.6. The oxide thickness, the fin width, and the fin height are fixed at 1.2 nm, 20 nm and 50 nm, respec-tively. Figures 2.7(a) shows a 3D doping profile and the corresponding refined mesh of the device, where the color of the mesh indicates the assigned doping concentration at mesh-ing lines. The fin height = 50 nm and the fin angle = 70o. Plots of the 3D simulated
on-2.3 : A 25-nm FinFET Simulation and Calibration 35
Figure 2.6: Three-dimensional schematic plots for the (a) bulk FinFETs and (b) SOI FinFETs. Θ is the fin angle and the inset shows a 2D cutting-plane extracting from the center of channel.
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Figure 2.7: (a) A plot of the 3D doping profile of the round-top-gate bulk FinFET. The left plot is the contour of doping profile and the right one is the corresponding mesh. (b) The left plot is the on-state potential of the round-top bulk FinFET and the right one is the off-state potential.
2.3 : A 25-nm FinFET Simulation and Calibration 37
Figure 2.8: Plots of the 2D cutting plane of the simulated on-state (VD= 1.0 V and VG= 1.0 V) (a) potential and (b) electron density at the center of channel of the 30 nm-height bulk FinFET.
The fin angles are the 90o, 80o, and 70o, respectively.
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Figure 2.9: Plots of the 2D cutting plane of the on-state (a) potential and (b) electron density at the center of channel of the 40 nm-height bulk FinFET. The fin angles are the 90o, 80o , and 70o, respectively.
2.3 : A 25-nm FinFET Simulation and Calibration 39
Figure 2.10: Plots of the 2D cutting plane of the on-state ((a) potential and (b) electron density at the center of channel of the 50 nm-height bulk FinFET. The fin angles are the 90o, 80o, and 70o, respectively.
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Table 2.1: Material parameters setting for silicon, poly-silicon, SiO2 and Si3N4. The epsilon is the ratio of the permittivities of material and vacuum.
Model Silicon Poly-Si SiO2 Si3N4
Epsilon 11.7 11.7 3.9 7.5
Heat Capacity (J/(kg-K)) 705 705 733 710.6
Bandgap (eV) 1.17 1.17 9 4.7
Thermal conductivity (W/(K-cm)) 1/(0.03+1.56e-3*T+ 1.5 0.014 0.185 1.65e-6*T2)
Constant Mobility (cm2/(V-s)) electron: 200*(T/300)−2.5 hole: 70*(T/300)−2.2
(the drain voltage VD = 1.0 V and VG = 1.0 V) and off-state (VD = 0.05 V and VG = 1.0 V) electrostatic potentials are shown in Fig. 2.7(b) for reference. For VD = VG = 1.0 V, contour plots of the potential and electron density (the 2D cutting planes along the center of channel) are shown in Figs. 2.8(a) and 2.8(b). The plots are device with three different angles of fin-taper: 70o, 80o, and 90o (from the left plot to the right one). Nonuniform dis-tributions of the potential and current density along the longitudinal direction are observed.
This a direct result of donor’s and bias’ impacts on the channel along the direction of the fin top to bottom. The potential attains the minimum value at the fin bottom, which increases rapidly toward the fin top. For the same distance, the larger potential associated with the larger fin taper angle is perceived from the fin bottom. The current density is reduced when the distance (from the top fin) is broadened; similarly, it has the minimum value at the fin
2.3 : A 25-nm FinFET Simulation and Calibration 41
bottom. For the device with the fin height = 30 nm, we find that the case of 90o, shown in Fig. 2.8, exhibits the most uniform distribution of the potential in the center of channel.
The potential decreases more quick with a more slanted fin angle, which leads to a stronger longitudinal electric field and may degrade the device performance. Similar results can be observed for the cases of fin height = 40 nm and 50 nm, as shown in Figs. 2.9 and 2.10.
For VD = VG = 1.0 V, the distributions of potential and electron density for device with the fin height = 30 nm (see Fig. 2.11(a)) and 50 nm (see Fig. 2.11(b)) are extracted according to the 1D cutting line, as shown in the inset of Fig. 2.4(b). The plots are device with three different angles of fin-taper: 70o, 80o, and 90o. Non-uniform distributions of the potential and electron density along the longitudinal direction are observed. This is a direct result of donor’s and bias’ impacts on the channel along the direction of the fin top to bottom. The potential attains the minimum value at the fin bottom, which increases rapidly toward the fin top. For the same distance, the larger potential associated with the larger fin taper angle is perceived from the fin bottom. The electron density is reduced when the distance (from the top fin) is broadened; similarly, it has the minimum value at the fin bottom. For the device with the fin height = 30 nm, shown in the left plot of Fig. 2.11(a), the case of 90o(i.e., the solid lines) exhibits the most uniform distribution of the potential in the center of channel. The potential decreases more quick with a more slanted fin angle, which leads to a stronger longitudinal electric field and may degrade the device performance.
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Figure 2.11: Plots of 1D cutting lines of the potential and electron density at the center of channel. The device is with the fin height of (a) 30 nm, and (b) 50 nm, where the solid line is the result of 90o, the dotted line is for the 80o, and the dashed line is for the 70o. The circled windows indicate the regimes where nearly constant potential and electron density are occurred in device channel.
2.3 : A 25-nm FinFET Simulation and Calibration 43
Similar results can be observed for the cases of fin height 50 nm. Moreover, it is found that the variation of potential almost keeps constant within the longest distance inside the channel region. The potential variation is significant when the fin angle is decreased, and the case of 70o (the dashed lines) possesses the largest potential variation among three angles. The variation is even more appreciable when the fin height is increased. For the different fin angles and fin heights, the right plots of Figs. 2.11(a) and 2.11(b) disclose the variation of the electron density versus the distance from the fin bottom. The variation of this physical quantity predicts the same trend as depicted above. It is found that the device with an approximately ideal fin angle (i.e, the fin angle approaches to 90o) behaves the most uniform distribution of the examined physical quantities within the device channel.
Plots of the drain current versus the gate voltage for the three fin angles and two fin heights are shown in Fig. 2.12(a). The case for the fin height of 30 nm, as shown in the left plot of Fig. 2.12(a), allows a larger variation of the fin angle, compared with the result of the fin height = 50 nm. It means that the fin height of 30 nm maintains a highest ratio of the on- and off-state currents and implies better performance. The parameters of short-channel effect versus the fin angle are calculated accordingly, as shown in Fig. 2.12(b). A larger taper angle is necessary for fabrication of nanoscale bulk FinFETs to obtain robust electrical characteristics. Besides, Fig. 2.12(b) implies that a smaller fin height is essential for the device of 25 nm gate length. The calculated SS suggests that an increase of the fin
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Figure 2.12: (a) The ID-VGcurves for the device for different fin angles and heights. The solid lines are the result of 90o, the dotted lines are for the 80o, and the dashed lines are for the 70o. (b) Results of SS (the left plot) and DIBL (the right one) versus the fin angle, where the solid lines are the result of 30 nm, the dotted lines are for the 40 nm, and the dashed lines are for the 50 nm.