3.4 Calibration and Verification
The device is simulated by solving a set of 3D Poisson equation and electron-hole current continuity equations with quantum corrections [99-103]. A step function, NA, is used to define the concentration and positions of dopants.
NA= is the number of dopants in the device channel; NAdopant is the associated doping concen-tration for a dopant within a box. Then, NA is substituted into the source of the Pois-son equation and solved with the electron-hole current continuity equations and density-gradient quantum correction equations simultaneously for device characteristics. Notably, in ”atomistic” device simulation, the resolution of individual charges within a conventional drift-diffusion simulation using a fine mesh creates problems associated with singularities in the Coulomb potential [81-83]. The potential becomes too steep with fine mesh and therefore the majority carriers are unphysically trapped by ionized impurities and the mo-bile carrier density is reduced [81-83]. Thus, the density gradient approximation is used
68 Chapter 3 : Simulation of Intrinsic Parameter Fluctuation
to handle discrete charges by properly introducing the related quantum mechanical effects [99-103]. All statistically generated discrete dopants are advanced and incorporated into the 3D device simulation under our parallel computing system [109-112]. Such large-scale simulation approach allows us to explore the electrical characteristic fluctuations induced by randomness of dopant number and position in the channel region concurrently.
Fig-Figure 3.11: Potential profiles for (a) classical (b) and quantum potential with different mesh size.
ures 3.11(a) and 3.11(b) illustrate the mesh size dependence of the classical and quantum mechanical potentials for a single discrete dopant within the silicon channel. In the ”atom-istic” simulation, the key point to study random impurities induced fluctuation relies on how to introduce the microscopic non-uniformity of localized impurity distributions inside
3.4 : Calibration and Verification 69
Figure 3.12: Meshing and dopant distribution for (a) long channel and (b) nanoscale transistors. The fine mesh in nanoscale transistor creates problems of singularities in the Coulomb potential and un-physically trap majority carriers.
the device. In conventional drift-diffusion approach for a large device size, the number of impurities included in each mesh exceeds one and the equivalent doping concentration does not change abruptly at every mesh node. Also, the dopant density at each mesh node changes gradually and the non-uniformity of impurity arrangement is averaged, as shown in Fig. 3.12(a). However, for the nanoscale transistor, the corresponding number of im-purities is significantly reduced. Most meshes contain no dopant or, at most, one dopant.
The dopant density at each mesh node changes its order of magnitude and behaves like a
70 Chapter 3 : Simulation of Intrinsic Parameter Fluctuation
-function, as shown in Fig. 3.12(b). The resolution of individual impurities for the con-ventional drift-diffusion simulation using a fine mesh creates problems of singularities in the Coulomb potential, as shown in Fig. 3.11(a). The sharp Coulomb potential wells may un-physically trap majority carriers, reduce the mobile electron concentration, modify the depletion region, and alter the threshold voltage. Therefore, the density gradient quantum correction [99-103] is used to handle the discrete dopant effect by properly introducing the related quantum mechanical effects, as plotted in Fig. 3.11(b). The quantum mechanical potential show less sensitivity to the mesh size and is quite similar for mesh spacing below 0.5 nm. We notice that the potential barrier of the Coulomb well is about 45 mV, which roughly corresponds to the ground state of a hydrogenic model of an impurity in silicon.
To extract the experimental data of σVth,RDF, the σVth,total and σVth,P V E are first di-rectly measured from experimental data. Since the mean gate length deviation, line edge roughness and random dopant distribution are the major variation sources of threshold volt-age. The σVth,RDF thus can be extracted from the approximated equation of Eq. 3.1. No-tably, the equation implies two important insights: σVth,totalreduction more relies on dom-inant factor improvement and the 2nd order factors will not impact the derived value of σVth,RDF. For example, assuming the σVth,RDF and σVth,P V E are 40 and 30 mV, respec-tively, the σVth,total is 50 mV. The 16% reduction of σVth,RDF achieves 16% reduction of σVth,total; however, it requires the 31% reduction of σVth,P V E to obtain the same σVth,total.
3.4 : Calibration and Verification 71
Moreover, even with an addition fluctuation sources, 20 mV, is introduced. The σVth,total is around 52 mV, which indicates the 2ndorder factors will not impact the derived value of σVth,RDF.
Figure 3.13: (a) Extracted non-strain mobility versus doping
concentration at 0.3 and 1 MV/cm vertical field, and (b) scaling of average channel dopant numbers versus channel size.
The employed physical model is first calibrated with experiment data. The mobility model is quantified with device measurements for the best accuracy. The used mobil-ity model can generate mobilmobil-ity that is in good agreement with the extracted mobilmobil-ity, as shown in Fig. 3.13(a). The low-field electron mobility at 0.3 MV/cm is greatly reduced with increasing doping concentration. That is why we limit our channel doping concentration
72 Chapter 3 : Simulation of Intrinsic Parameter Fluctuation
Figure 3.14: (a) Experimentally extracted σVth,RDF, and
discrete-dopant simulation (*, Lg = W = 20 nm, EOT = 1.2 nm) for various devices with nominal Lg from 55 nm down to 20 nm. The width is fixed and the length is varying to give the range of values of (WL)−0.5. The sample size for each data point of Vthis around 100 points.
(b) The extracted σVth,P V E for c and d conditions. The value was normalized against the σVth,P V E of nominal Lg case in d condition.
3.4 : Calibration and Verification 73
Table 3.1: The trend of Vthfor technology scaling. The nominal Lg cases in table are nominal gate lengths for each technology node respectively.
EOT (nm) Channel Doping (cm−3) Nominal Lg(nm) Width (nm)
a 2.4 1.0×1018 55 1000
b 1.8 3.0×1018 35 1000
c 1.2 5.0×1018 20 200
d 1.2 5.0×1018 20 20
Table 3.2: Summary of experimental and simulation results of discrete dopant fluctuated 20-nm-gate planar CMOS transistors.
Lg (nm) Width (nm) Data Source Channel Doping (cm−3) EOT(nm) Vth,RDF (mV)
20 200 experimental 5.0×1018 1.2 17
20 200 simulation 5.0×1018 1.2 17.7
20 20 experimental 5.0×1018 1.2 40
20 20 simulation 5.0×1018 1.2 39
74 Chapter 3 : Simulation of Intrinsic Parameter Fluctuation
around 1×1018 cm−3. Less channel doping concentration may reduce σVth,RD, but chan-nel dopants will quickly approach to single-digit number, as shown in Fig. 3.13(b). The random-dopant-induced Vthfluctuation, σVth,RDF, has then been experimentally extracted, as shown in Fig. 3.14(a). Discrete-dopant simulation for Lg= width (W) = 20 nm (data rep-resented with symbol *, as shown in Fig. 3.14(a)) in good agreement with the experimental data, which confirms the channel doping is randomly distributed as statistically modeled.
As shown in Fig. 3.3, more than 100 cases are required for a set of Lg and width; we no-tice that each 3D simulation case may take about 3 to 7 days for final convergent result.
Without loss of generality, due to the heavy computing resource, we select the most critical case (i.e., length = width = 20 nm) for comparison between simulation and measurement.
Figure 3.14(b) shows the extracted σVth,P V E of c and d conditions. The σVth,P V E con-tains the contribution from the mean gate length deviation and the line edge roughness. In our experimental data, the σVth,P V Eincreases as the (WL)−0.5increased, and it has similar trend, compared with σVth,RDF. Table 3.1 summaries the corresponding parameters for all cases in Fig. 3.13. Figure 3.13(a) shows the extracted mobility versus the doping concen-tration from samples of the cases a and b, as shown in Fig. 3.14(a). Table 3.2 summaries the experimental and simulation results of discrete dopant fluctuated 20-nm-gate planar CMOS transistors. The summary corresponds to Fig. 1.2 in previous section. The experi-mentally extracted σVth,RDF for devices with 200-nm- and 20-nm-width are about 17 and
3.5 : Summary 75
40 mV. The result of developed simulation metrology is similar to the experimental data, which confirms the reliability of this approach. The mathematical device simulation accu-racy is calibrated with full quantum mechanical simulation and energy level of impurities.
The accuracy of large-scale statistical methodology is verified by experimental data. The proposed simulation approach is convincing in study of nanoscale transistor variabilities.
3.5 Summary
For PVE, the σLg,P V E can be obtained from extracted the line-edge shape of a device gate from SEM pictures or through the statistically generated line-edge profile. The process-variation-effect includes the gate length variation and line edge roughness, whose magni-tude follows the ITRS roadmap. The look-up table of the threshold voltage versus the gate length from threshold voltage roll-off slope is provided to estimate the effect of σLg,P V E in σVth,P V E. The simulation of random dopant effect relies on the generation and assignment of discrete impurities in transistors. The large-scale generation approach is similar to the manufacturing process. Then the generation approach has been extended by using ”atom-istic” process simulation and SIMS profile. After the dopant generation, the dopants are assigned into device channel region by using step function for discrete dopant simulation.
The simulation result has been verified with experimentally measured data. The workfunc-tion fluctuaworkfunc-tion is an emerging source of fluctuaworkfunc-tion accompanied by the high-κ/metal-gate
76 Chapter 3 : Simulation of Intrinsic Parameter Fluctuation
technology. In this thesis, an statistical generation approaches has been applied and used for device and circuit fluctuation analysis. However, we have to notice the simulation ap-proach can be further improved by incorporating the nucleation and growth of metal and grain boundary effect. Based on the large-scale statistic approaches, the fluctuation of de-vice characteristics can be obtained then used for evaluation of circuit reliability.
Chapter 4
Random-Dopant-Induced
Characteristics Fluctuation in Vertical-Channel Devices
ITRS roadmap [1] has forecasted the transition from planar MOSFETs structure to ver-tical channel device structure and bulk silicon substrate to insulator substrate for perfor-mance enhancement and leakage current reduction. Though the un-doped SOI devices can prevent the random-dopant-induced fluctuation, they may suffer from more signifi-cant SCEs. Thus, the channel doping must be employed to alter the threshold voltage
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Chapter 4 : Random-Dopant-Induced Characteristics Fluctuation in Vertical-Channel Devices and provide the promising electrical characteristics in today’s semiconductor manufactur-ing processes. Consequently, characteristic fluctuation that is induced by discrete dopants is important in these nanoscale MOSFETs, which with fascinating structures. Since the random dopant fluctuation is the dominating factor in device variability, this chapter in-vestigates the discrete-dopant-induced device fluctuation in bulk FinFETs and SOI devices from single-gate to surrounding-gate nanowire transistors by using 3D atomistic device simulation with density-gradient quantum correction on our parallel computing systems.
An insight into the intrinsic fluctuation and the mechanism of immunity against fluctuation in multiple-gate devices has been provided.