Background

The rapid progress of complementary metal-oxide-semiconductor (CMOS) integrated circuit technology since the late 1980’s has enabled the Si-base microelectronics industry to simultaneously meet several technological requirements to fuel market expansion. These requirements include performance (speed), low static (off-state) power and a wide range of power supply and output voltages [1]. This has been accomplished by developing the ability to perform a calculated reduction of the dimensions of the fundamental active device in the circuit, following the “Moore’s law”, doubling about every two or three years since about 1980 [2]-[4]. The result has been a dramatic expansion in technology and communications markets including the market associated with high-performance microprocessors as well as low static-power applications, such as wireless systems.

It can be argued that the key element enabling the scaling of the Si-based metal-oxide-semiconductor field effect transistor (MOSFET) is the materials and resultant electrical properties associated with the dielectric employed to isolate the transistor gate from the Si channel for decades: silicon dioxide (SiO2). The use of amorphous, thermally grown SiO₂ as a gate dielectric offers several key advantages in

high-quality Si-SiO₂ interface as well as superior electrical isolation properties. In modern CMOS processing, defect charge densities are on the order of 10¹⁰ cm^-2, midgap interface state densities are ~ 10¹⁰ cm^-2eV^-1 and hard breakdown fields of 15 MV/cm are routinely obtained and are therefore expected regardless of the device dimensions. These outstanding electrical properties clearly present a significant challenge for any alternative gate dielectric candidate [5], [6].

Over the years, there have been several major evolutions in silicon digital logic technology. CMOS technology has become the most popular digital logic technology for all IC industry, owing to its low standby power dissipation and scaling properties.

Oxide thickness scaling has long been recognized as one of major keys for devices scaling. High drive current and thereby improved device performance can be achieved by reducing oxide thickness. It suggests that at the current rate of progress, Fig. 1.1 stresses the urgent need for a nitrided oxides (SiO_xN_y) and high dielectric constant (κ) gate dielectrics for low stand-by power application after the year 2002 and 2006, respectively [7]. Besides, the direct tunneling current increases exponentially by about one order of magnitude for every 0.2nm ~ 0.3nm reduction in oxide thickness. This additional leakage current not only causes increased power dissipation but also may affect the circuit functionality due to the decreased operation margins.

For this reason, several alternative materials for silicon dioxide are currently being investigated. Ultrathin nitrided oxides are the leading candidates to replace pure SiO₂ [8]-[14]. Figure 1.2 shows the expected equivalent oxide thickness (EOT) trends from the published 2003- ITRS roadmap. It suggests nitrided oxides can extend SiO2

limitation to 2006 without massive change in production technologies. Nitrided oxides exhibit several properties superior to those of conventional thermal SiO2, the more important being suppression of boron penetration from the poly-Si gate and enhanced

reliability. Nitrogen also reduces hot-electron-induced degradation [15]. The dielectric constant of the oxynitride increases linearly with the percentage of nitrogen from κ (SiO2) = 3.9 to κ (Si3N4) = 7.8 [16], though one should note that most SiOxNy films grown currently by thermal methods are lightly doped with N (< 10 at.%) and therefore have a dielectric constant only slightly higher than that of pure SiO₂. The other potential candidates to replace silicon dioxide are high-κ materials, including aluminum oxide (Al₂O₃), hafnium oxide (HfO₂) and zirconium oxide (ZrO₂) etc [17]-[20]. The most benefic for high-κ dielectrics is leakage current reduction by several orders of magnitude at the same EOT compared to SiO₂. However, in device performance point of view, a suitable gate dielectric candidate should also meet the other requirements, including high thermal stability, high carrier mobility, small oxide charges, good stress immunity and CMOS compatible.

On the other hand, high-κ dielectrics are paid much attention on the flash memory applications [21]-[27]. The thickness of inter-poly dielectric (IPD) and tunnel dielectric (TD) in stacked-gate flash memory had meet intrinsic limitation [28]. It is not sufficient to meet the stringent data retention requirement of IPD while applying thermal or CVD oxynitride technologies due to the unavoidable leakage current [29]-[32]. By increasing the floating gate coupling ratio, high-κ IPD can lead to a high electric field across tunnel oxide (TOX) even at very low control gate voltage. For the tunnel dielectric engineering of stacked-gate flash memories, the issue is closely related to dielectric material selection itself. Flash tunnel dielectric has two roles. One is a barrier to suppress charge leakage under read and retention. Second role is a charge transfer path. In order to avoid trap-assisted tunneling via one trap site, the minimum TOX thickness of conventional FG structure will be limit to 8 nm. This limits the tunnel SiO2 scaling and program/erase voltage reduction. Nitrided oxide

have been intensively studied, but so far only 5 to 10 times improvement for low field leakage is achieved [33]. This is not enough, because it only achieves 1 nm reduction even with heavy nitridation.

To successfully employ the high-κ IPD and TD into flash memory, one must take charge retention issues into consideration and make sure that the barrier height (ϕB) between Si and the new adopted high-κ dielectrics should be larger than 1.5eV for effectively suppressing the loss of floating gate charges through electron thermal emission [33]. Usually, dielectrics with higher κ inherently have lower ϕB. Therefore a trade-off between dielectric constant and barrier height is inevitably required in trying to implement the high-κ dielectrics in flash memories.