Program/Erase Characteristics of Flash Memories with HfO 2 IPD and

The CHE current injected to the FG of the stacked-gate flash memories with

HfO2 IPD and high-κ TDs is compared in Fig. 5.5(a). By replacing SiO2 TOX to high-κ tunnel dielectrics, the injected hot electron current from the substrate to the FG is obviously increased. Figure 5.5(b) shows the calculated CHE injection efficiency of the stacked-gate flash memories with HfO₂ IPD and high-κ TDs. Similarly, the enhanced injection efficiency is obtained by increasing the κ-value of the tunnel dielectrics. The CHE programming times as a function of VGS for various TDs are shown in Fig. 5.6. For the 10 µs programming time, the control gate voltage can be reduced by 16%, 18% and 27% with replacing SiO2 TOX to Si3N4, Al2O3 and HfO2

TD, respectively. Although the electric field on high-κ tunnel dielectrics is lower than SiO₂ TOX, enhanced impact ionization rate and lower ϕB contribute to higher CHE programming speed. As a result, the flash memories with HfO2 IPD and high-κ TDs are suitable to supplant presently tunneling oxide in NOR-type array architectures.

Figure 5.7 compares the FN tunneling current injected to FG under CFN programming schemes of the stacked-gate flash memories with HfO2 IPD and high-κ TDs. Injected FN current reveals a stronger dependence on the permittivity of the TDs than HE current. More than 10 times FN current reduction is observed while replacing tunneling oxide to high-κ TDs. Figure 5.8 shows the relationships between CFN programming time and V_GS for flash memories with different TDs. Obviously, the degradation of CFN programming speed can be ascribed to the reduced tunneling current from substrate into the FG. Compared to the results in Fig. 5.6, the benefit of employing high-κ TDs is obviously only effective in CHE programming rather than in CFN programming. This is ascribed to that FN tunneling current is exponentially dependent on the electric field, the smaller electric field on high-κ TDs reduces electron injection efficiency than SiO2 TOX. Therefore, the application of the high-κ TDs in the stacked-gate flash memories with CFN programming is unbeneficial,

contrary to the CHE programming.

Figure 5.9(a) compares the programmed state IPD electric field of the stacked-gate flash memories as a function of VGS with floating drain and substrate.

Increasing the κ-value of the TDs will lead to undesired IPD electric field increment, the high-κ TDs may deteriorate erase window through charge injection between the FG and the control gate. As seen in Fig. 5.9(b), the flash memories with high-κ TDs also reduce electric field on the TDs and degrade erasing speeds, similar to the CFN programming. Referring to Fig. 4.11, large positive electric field for flash memories with high-κ TDs will limit electron in the FG to be erased through tunnel dielectrics while enhance unwanted electron injection from control gate to FG. Consequently, flash memories with HfO₂ IPD and high-κ TDs are therefore expected to reduce erasing speed as well as narrow down erasing window. Figure 5.10 compares the FN tunneling current ejected from the FG under SFN erasing schemes of the stacked-gate flash memories with HfO2 IPD and high-κ TDs. Ejected FN current reveals a strong dependence on the permittivity of the TDs. Similar to the CFN programming, larger than 80 times FN current reduction is observed while replacing SiO2 TOX to high-κ TDs during erase. The SFN erasing time verse VG for flash memories with HfO2 IPD and high-κ TDs is shown in Fig. 5.11. Employing high-κ dielectrics as the TD also tremendously degrades erasing speed directly ascribed to the decreased gate coupling ratio, which is larger than 18% and 48% for Al₂O₃ TD and HfO₂ TD, respectively. In summary, operation voltage reductions are listed in Table 5.2.

Consider CHE programming scheme, the flash memories with HfO2 IPD and high-κ TDs exhibit larger than 18% and 27% voltage reduction for Al2O3 TD and HfO2 TD, respectively. The improvement is apparently greater than the flash memories with high-κ IPDs. Our simulation results clearly indicate stacked-gate flash

memories with HfO2 IPD and high-κ TDs can be used to replace conventional NOR-type flash cells, in terms of control gate voltage scaling and operation speed promotion.

5.4 Summary

The effects of high-κ TDs on program/erase performance of the stacked-gate flash memories are investigated. The results are quite contrary with respect to high-κ IPD. Due to the reduced gate coupling ratio, the programming/erasing speed of the stacked-gate flash memories with high-κ TDs by using FN tunneling is helpless in operation voltage reduction. On the other hand, the increased electric field on HfO₂ IPD would produce excess charge loss and narrow the operation window between programmed and erased state. Although the electric field on high-κ tunnel dielectrics is lower than SiO₂ TOX, enhanced impact ionization rate and lower ϕB contribute to higher CHE injection current and efficiency. Consequently, high-κ TDs are only effective for the memories programmed/erased with hot electron injection rather than FN tunneling. Due to the contrary improvement in programming/erasing schemes with respect to high-κ IPDs described in Chapter 4, high-κ TDs are suitable for next decade NOR-type stacked-gate flash memories.

Table 5.1 Dielectric constants and conduction band offsets with respect to Si of the TD materials with fixed HfO2 IPD for simulated stacked-gate flash memories.

TD Thickness κ ∆EC (ϕB)

SiO2 100Å 3.9 3.2

Si₃N₄ 100Å 7.5 2.1

Al2O3 100Å 9 2.8

HfO2 100Å 25 1.5

Table 5.2 Operation voltage reduction of stacked gate flash memories with HfO2 IPD and high-κ TDs.

HfO₂ Al₂O₃ Si₃N₄ SiO₂

GCR 0.422 0.662 0.701 0.814

DCR 0.056 0.042 0.039 0.029

SCR 0.236 0.138 0.122 0.076

GCR Degradation -48.03% -18.37% -13.72%

DCR Degradation -86.29% -39.80% -30.77%

SCR Degradation -206.89% -79.71% -59.04%

VGS 7.33 8.25 8.42 10.05 10µs CHE

Program

Improvement 27.08% 17.91% 16.19%

VGS 13.72 10.92 9.97 7.65 10µs CFN

Program

Degradation -79.35% -42.75% -30.33%

VGS -11.01 -8.83 -7.82 -6.23 0.1ms SFN

Erase

Degradation -76.73% -41.73% -25.52%

0 2 4 6 8 10 12 14 16 18 20

Fig. 5.1 (a) IPD (b) TD electric field as a function of control gate voltages of erased state stacked-gate flash memories with HfO₂ IPD and high-κ TDs under V_D = V_B = V_S

= -9.0V. High-κ TDs can increase IPD electric field as well as reduce TD electric field.

0.0 0.5 1.0 1.5 2.0

Fig. 5.2 (a) Linear region (b) saturation region transfer characteristics of stacked-gate flash memories with HfO₂ IPD and high-κ TDs. The flash memories with HfO2 IPD and high-κ TDs not only depict the degraded subthreshold swing but also exhibit significantly large off-state current.

0 1 2 3 4 5

Fig. 5.3 Output characteristics of stacked-gate flash memories with HfO2 IPD and high-κ TDs.

Fig. 5.4 Substrate current of stacked-gate flash memories with HfO₂ IPD and high-κ TDs. Maximum substrate current is substantially dependent of the κ-values of TDs.

0 2 4 6 8 10 12 14 16 18 20

Fig. 5.5 (a) CHE current injected to FG (b) CHE injection efficiency as a function of control gate voltages of stacked-gate flash memories with HfO₂ IPD and high-κ TDs at V_DS = 5.0V. Flash memories with high-κ TDs dramatically enhance injection efficiency than SiO2 TOX.

0 2 4 6 8 10 12 14 16 18 20

CHE Programming Time ( sec )

VGS ( V )

Fig. 5.6 CHE programming time as a function of control gate voltages of stacked-gate flash memories with HfO₂ IPD and high-κ TDs at V_DS = 5.0V.

Fig. 5.7 CFN current injected to FG as a function of control gate voltages of stacked-gate flash memories with HfO₂ IPD and high-κ TDs at V_DS = 5.0V.

0 2 4 6 8 10 12 14 16 18 20 1E-10

1E-9 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 0.01 0.1 1 10 100 1000

HfO2 IPD / High-κ TD VD = V

B = V

S = -9.0 V

CFN Programming Time ( sec )

VGS ( V ) SiO2

Si3N

4

Al₂O₃ HfO2

Fig. 5.8 CFN programming time as a function of control gate voltages of stacked-gate flash memories with HfO₂ IPD and high-κ TDs at V_D = V_B = V_S = -9.0V. Obvious degradation in CFN programming speed for high-κ TDs is indicated.

0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20

Fig. 5.9 (a) Absolute IPD (b) TD electric field as a function of control gate voltages of programmed state stacked-gate flash memories with HfO₂ IPD and high-κ TDs under V_S = 5.0V. Drain and substrate terminals are floating. High-κ TDs would increase IPD electric field as well as reduce TD electric field.

0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20

Fig. 5.10 SFN current ejected from FG of stacked-gate flash memories with HfO2 IPD and high-κ TDs under V_S = 5.0V, floated drain and substrate terminal.

0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20

Fig. 5.11 SFN erasing time of stacked-gate flash memories with HfO₂ IPD and high-κ TDs. High-κ TDs crucially deteriorate SFN erasing speed.

CHAPTER 6

Study of Surface NH

Nitridation on the Trapping Characteristics and Dielectric Reliabilities of Al

O

IPD

6.1 Introduction

Fast low-power nonvolatile memories are required for future wireless communication products. In the recent flash memory technologies, short program/erase times and operating voltage reductions are the most important issues to realize high speed/low power operation [28], [89]-[91]. For EEPROM and flash memory devices, the inter-poly dielectric (IPD) requires a high charge-to-breakdown (QBD), high breakdown field and low leakage current to obtain good data retention characteristics [92]-[94]. It is not sufficient to meet the stringent data retention requirement of IPD while applying thermal or CVD oxynitride technologies due to the unavoidable leakage current [29]-[32], [95]. In order to accomplish this without a trade-off between low power and high speed operations, high coupling ratio should be achieved by increasing the floating gate capacitance [89], [90], [96]-[103].

There are three different approaches can be used to increase coupling ratio. First, decrease the IPD thickness. Oxide/nitride/oxide (ONO) multi-layered films had been extensively investigated and frequently used as the dielectric layer in the flash memory devices and other applications [104]-[106]. However, decreasing the

thickness of the IPD to increase the coupling ratio may cause serious leakage and reliability problems which are fatal in the retention time of flash memories. Secondly, increase the area of the IPD capacitor. High capacitive-coupling ratio cell [96]-[98], 3-dimension interpoly dielectric [100], and hemisphere grain [101], [102] had been proposed to effective increase the capacitance area and lower the control gate bias.

Although the coupling ratio of above mentioned cell structures could be dramatically improved, they must be fabricated with many additional process steps for fabrication such complex structures and be difficult to control well. The final approach is to increase the dielectric constant (κ) of IPD materials [22], [23], [27], [107]-[114].

Therefore, it is straightforward and effective to incorporate alternative high dielectric constant (high-κ) materials on nonvolatile memories to replace oxide/nitride/oxide IPD for increasing floating gate capacitance without increasing cell area and complexity of fabrication while suppressing charge loss.

In Chapter 4, we have demonstrated that the control gate voltage can be reduced greater than 30% with high-κ IPDs through MEDICI simulation. Among those potential candidates, aluminum oxide (Al₂O₃) is the most attractive for IPD applications in nonvolatile flash memories because of its higher conduction band offset with respect to the underlying poly-Si electrode and its higher permittivity with respect to Si3N4 [17], [21], [84], [85], [112], [115]. Previously, Lee et al. had been shown the benefits of using an Al₂O₃ IPD for low voltage/high speed flash memories in simulations [21]. In this chapter, the effect of surface NH3 nitridation on the electrical properties and reliability characteristics of dc reactive-sputtered (RS) Al₂O₃ inter-poly capacitors are studied. It is found that the incorporation of nitrogen on the bottom poly-Si surface can not only reduce leakage current by one order of magnitude, but also enhance the breakdown field and the QBD as well. This is ascribed to the

resultant smoother interface between the dielectric and the floating gate by surface nitridation and less electron traps in the bulk. Auger electron spectroscopy (AES) depth profile also shows that the surface nitridation can effectively eliminate inter-diffusion between Al2O3 IPD and underneath poly-Si.

6.2 Experimental Details

The n⁺-polysilicon/Al2O3/n⁺-polysilicon capacitors were fabricated on 6-inch p-type (100)-oriented silicon wafers. Silicon wafer was thermally oxidized at 950^oC to grow a 2000Å buffer oxide. 2000Å bottom polysilicon film (Poly-I) was deposited on the buffer oxide by low pressure chemical vapor deposition (LPCVD) system using SiH₄ gas at 620^oC and subsequently implanted with phosphorous at 5×15cm^-2, 20keV, then activated with RTA at 950°C for 30s. Prior to the growth of Al2O3 IPDs, the native oxide covered Poly-I was cleaned by the conventional RCA cleaning and diluted HF etching in sequence for the removal of particles and native oxides. The surface of Poly-I prepared in this matter was known to be contamination free and terminated with atomic hydrogen. After being wet cleaned and dipped in HF solution, several samples were subjected to ammonia (NH3) nitridation in the LPCVD furnace at 800°C for 1hour. Then, 10nm Al2O3 IPD was deposited by reactive sputtering (RS) in an Ar/O2 ambient. Annealing of Al2O3 IPDs was carried out by rapid thermal annealing at 800^oC in an O₂ atmosphere for 30s. Subsequently, a 2000Å top polysilicon layer (Poly-II) was deposited by LPCVD and implanted with phosphorous at 5×15cm^-2, 20keV. Dopants were then activated with RTA at 950°C for 30s. Finally, 5000Å TEOS oxide passivation and Al metal pads were defined. The cross-sectional

view and key process steps of Al₂O₃ inter-poly capacitor with surface NH₃ nitridation and post-deposition oxygen annealing are shown in Fig. 6.1 and 6.2, respectively.

The equivalent oxide thickness (EOT) was obtained from the high frequency (100kHz) capacitance-voltage (C-V) measurement using a Hewlett-Packard (HP) 4284. Moreover, the physical thickness was estimated by high resolution transmission electron microscopy (HRTEM). The electrical properties and reliability characteristics of the inter-poly capacitors were measured using a HP4156C semiconductor parameter analyzer. The atomic concentrations and depth profiles of the Al₂O₃ IPD were extracted by AES. The blanket wafers with Al2O3 dielectric deposition on top of the Poly-I annealed at various PDA temperatures were also prepared for surface roughness measurement by atomic force microscopy (AFM).

6.3 Results and Discussions

In this chapter, the effects of surface NH3 nitridation on the dc reactive-sputtered Al₂O₃ IPD are investigated in terms of leakage current, surface roughness and dielectric reliabilities.

6.3.1 Investigation of Surface NH3 Nitridation Effects on the RS Al2O3 IPD

The current density-effective electric field (breakdown voltage/EOT) (J-E) characteristics of the 800^oC-annealed Al₂O₃ inter-poly capacitors with and without NH3 nitridation on the Poly-I surface at 800°C for 1hr are seen in Fig. 6.3(a). The J-E curves reveal a rapid rise in leakage current at electric field beyond 5 MV/cm due to

Fowler-Nordheim (FN) tunneling through the Al₂O₃ IPD. It is found that the sample with NH3 nitridation results in an almost one order of magnitude reduction in positive-biased leakage current density, compared to the sample without NH₃ nitridation. Similarly, a leakage current with 10 times reduction is also observed in negative polarity. Figure 6.3(b) indicates C-V curves of 800^oC-annealed Al₂O₃ inter-poly capacitors with and without surface NH3 nitridation. Comparing to conventional MOS-capacitors, inter-poly capacitors have large minimum capacitance due to heavy doping in Poly-I. The EOT of sample with and without nitridation is 4.6nm and 5.6nm, respectively. Surface nitridation can effectively suppress the interfacial layer (IL) growth, and results in 1nm EOT thinning, which can be evidenced by HRTEM images shown in Fig. 6.4.

It is important to monitor both the leakage current uniformity and breakdown field of IPD to inspect the charge loss conditions through low and high electric field for flash memories biased at read and program/erase scheme, respectively. According to the simulated electric field shown in Fig. 4.2, leakage current density at 3 MV/cm and 8 MV/cm is chosen to be the indicators of charge loss through Al₂O₃ IPD at read and program scheme, respectively. Figure 6.5 compares the Weibull distributions of the leakage current density of Al₂O₃ inter-poly capacitors after 800^oC PDA with and without NH3 nitridation in both polarities. Strong polarity dependence between positive and negative bias is evident in Al₂O₃ IPD with and without nitridation, leakage current at positive bias is higher than negative bias, which can be partially explained by asymmetric band diagrams for electron injection. Although the leakage current reduction at low electric field is inconspicuous, surface nitridation can effectively suppress high electric field leakage current, especially for positive gate voltage. The results apparently demonstrate Al2O3 IPD with surface nitridation can

effectively reduce charge loss from floating gate to control gate as well as carrier injection from control gate to floating gate, better retention and disturb characteristics are expected by replacing ONO IPD to Al₂O₃ IPD.

Figure 6.6 examines the Weibull distributions of the effective breakdown field in the Al2O3 inter-poly capacitors after 800^oC PDA with and without surface NH3

nitridation for both polarities. A breakdown field improvement of more than 2 MV/cm is clearly observed on the nitridated samples for both positive and negative polarities.

Higher breakdown is helpful to reduce charge transportation path between control gate and floating gate. Dielectric relaxation current (transient gate current) for the 800^oC-annealed Al₂O₃ IPDs with and without NH₃ nitridation was measured instantly after a 2V voltage step, which is shown in Fig. 6. 7. J(t) follows a t^-n dependence with n close to 1 for 10 decades of times, which can be explained by Curie-von Schweidler law and double potential well model [116]-[118]. Due to the asymmetry of the energy band structure, electron transport is easier in positive polarity than negative polarity.

As a result, positive polarity shows larger relaxation current. Moreover, samples with NH3 nitridation apparently reduce relaxation current, which can be ascribed to the reduced bulk defects. Al2O3 IPD with surface nitridation clearly suppresses the relaxation current due to smaller trapping density and trapping rate, as shown in below.

Figure 6.8(a) depicts the charge trapping curves of the 800^oC-PDA Al2O3

inter-poly capacitors with and without nitridation under a constant current stress (CCS) of 5 mA/cm² and 1 mA/cm², respectively, in both polarities. The increase in the absolute gate voltage is obviously coming from electron trapping. It is noted that the Al2O3 inter-poly capacitors with surface nitridation, albeit subjected to a larger stressing current, show a much smaller electron-trapping rate than those without

nitridation. Figure 6.8(b) demonstrates the corresponding Weibull distributions of Q_BD for two splits. Clearly, the Al2O3 inter-poly capacitor with NH3 nitridation has a nearly one order of magnitude improvement. This trend is fully consistent with the results in Fig. 6.8(a), i.e., higher trapping rate will lead to lower QBD. The relatively reduced electron trapping rate is also consistent to the suppressed dielectric relaxation current for the IPD with NH3 nitridation.

6.3.2 Conduction Mechanism of the RS Al2O3 IPD

Figure 6.9(a) shows the J-E characteristics of 800^oC-annealed Al2O3 inter-poly capacitors with and without NH₃ nitridation measured at four different temperatures, 25^oC, 75^oC, 100^oC and 125^oC. The effect on the leakage current as the temperature rises from room temperature to 125^oC is minor, which confirms that the FN tunneling dominates the conduction mechanism, rather than Frenkel-Poole tunneling. Moreover, despite measuring temperatures, positive-biased leakage current is always higher than negative-biased current. Effective barrier heights (ϕB) of the 800^oC-annealed Al₂O₃ IPD with and without NH₃ nitridation in both polarities are extracted in Fig. 6.9(b). In positive polarity, the ϕB of the Al₂O₃ IPD with and without NH₃ nitridation are 1.54eV and 1.25eV, respectively, from fitting the voltage dependence of the FN tunneling current by assuming effective electron mass in Al2O3 of being 0.2m0 [119].

Higher ϕB can reduce electron tunneling probability and lead to lower leakage current density. However, the barrier heights in negative polarity are 1.62eV with nitridation and 1.59eV without. The nearly identical ϕB value cannot account for the reduction of the lower leakage current of nitridated IPD in negative polarity, as compared with non-nitridated IPD. We ascribe this result to the small concentration of oxygen

o

further discussed later.

6.3.3 Polarity Dependence of the RS Al2O3 IPD

Although Poly-I and Poly-II have similar fabrication process, our results clearly indicate asymmetric polarity characteristics. The enhanced breakdown field and reduced leakage current of nitrided samples in positive polarity may be attributed to

Although Poly-I and Poly-II have similar fabrication process, our results clearly indicate asymmetric polarity characteristics. The enhanced breakdown field and reduced leakage current of nitrided samples in positive polarity may be attributed to