Chapter 3 Characteristics and Reliabilities of Sub-3nm Nitrided Oxides
3.3.2 Reliability Characteristics of Sub-3nm NIS Nitrided Oxides
Figure 3.4(a) displays the XPS depth profiles of NO-annealed nitrided oxide with 4×1015 cm-2 NIS dosage. Not alike to Fig. 2.6(a), pre-oxidation NIS will incorporate N into dielectric bulk rather than pile-up at interface. Figure 3.4(b) compares nitrogen distribution profiles with and without NIS. Without NIS, dielectric bulk is devoid of nitrogen. After post-oxidation NO annealing NIS nitrided oxides, more N will diffuse to interface, form Si3≡N bonding. Moreover, sample with 1×1015 cm-2 NIS not only exhibits higher peak concentration at interface, but also has tighter N distribution than samples with lighter NIS, which is beneficial to obtain an uniformly distributed reliabilities. Figure 3.5 indicates the leakage current density of 22Å N - and NO-annealed NIS nitrided oxides with and without nitrogen implantation
under constant voltage stress (CVS) at -4V for 100sec. The major difference between fresh and stressed curves occurs near flat-band conditions, as described in Chapter 2.
Comparing to gate oxides without NIS, apparent SILC increment for low and medium dose NIS is exhibited. However, there is almost no leakage current increase for heavy NIS during voltage stress. The reasons for dosage-dependent SILC immunity will be explained below.
Figure 3.6(a) compares transient trapping behavior of 22Å NO-annealed NIS nitrided oxides during CCS. It should be noted all samples show an obvious hole trapping characteristics. For NIS smaller than 1×1014 cm-2, pre-oxidation nitrogen implantation will enhance the hole trapping. As NIS increases to 1×1015 cm-2, the hole trapping becomes negligible. The trap generation rate as a function of injected charges is seen in Fig. 3.6(b). Similar trend is examined. Eliminated trap generation rate appears only at heavy N implantation case, i.e. 1×1015 cm-2. Figure 3.7(a) presents the time-dependent dielectric breakdown (TDDB) Weibull distribution of 22Å NO-annealed NIS nitrided oxides during CVS at -4.3V. Nitrided oxides with NIS less than 1×1014 cm-2 reveal poorer tBD than the samples without NIS due to the larger hole generation rate. As consistent to Fig. 3.6, heavy NIS is expected to exhibit the highest tBD. The Weibull slope is also dependent on the NIS dosage, which is plotted in Fig.
3.7(b). β shows a valley at the NIS dosage of 1×1013 cm-2 from residual implantation damage and a peak at 1×1015 cm-2 due to the tighten nitrogen distribution profiles in the dielectric bulk. As shown in Fig. 3.4(b), 1×1015 cm-2 NIS will retard oxidation rate and generate uniform N distribution, higher β is expected for heavy NIS. Although thinner oxide thickness of sample with 1×1015 cm-2 NIS would partially contribute to less SILC characteristics, only 3~4Å thickness reduction may not enhance SILC immunity significantly than samples with 1×1013 and 1×1014 cm-2 NIS. As a result, the
drastic SILC immunity improvement is accredited to uniform nitrogen distribution in the dielectric bulk.
In our study, NIS dosage smaller than 1×1014 cm-2 will slightly increase the oxidation rate due to insufficient post-oxidation annealing out the damage from ion bombardment, which is shown in Fig. 3.1. The residual damage may increase weak bonding during oxidation and result in less SILC immunity, enhanced trap generation rate and poor tBD. Inferior surface roughness will also response for degraded dielectric reliability, as seen in Fig. 3.8 and 3.9 for N2- and NO-annealed NIS nitrided oxides, respectively. On the other hand, samples with 1×1015 cm-2 NIS not only can use to grow multiple oxide thickness but also improve reliability significantly. The results are quite opposite to samples with lighter implantation dose, which can attribute to several reasons.
First, surface is abounded with N atoms for heavy NIS implantation dosage, which may easily replace the weak Si-O bonds damaged by ion bombardment in the transition region by the strong Si3≡N bonds during oxidation. Secondly, implantation would change interface morphology [70]. From HRTEM photos exhibited in Fig. 3.8 and 3.9, surface roughness is increased while NIS increases from 0 to 1×1014 cm-2, which may be due to faster oxidation rate and less N area density. On the other hand, surface RMS roughness is decreased to 0.87nm with further increasing NIS to 1×1015 cm-2. It can be seen that the nitrided oxide/silicon interface is very smooth and exhibits a highly uniform transition region from the crystalline silicon to the amorphorous nitrided oxide. This is beneficial for the electrical properties of the MOS device as described above. Surface roughness is also evidenced by AFM images and summarized in Fig. 3.10. A smoother interface is helpful in reducing the localized field and, hence, results in stronger SILC immunity and larger tBD. Thirdly, it is
known that SILC becomes negligible as the oxide thickness down to the direct-tunneling dominate regime. The heaviest NIS can retard oxidation rate significantly and grow the thinnest oxide, as seen in Fig. 3.2. In consequence, nitrided oxides with NIS dosage of 1×1015 cm-2 possesses stronger SILC immunity and better TDDB characteristics than others, regardless of post-oxidation N2- or NO-annealing.
3.4 Summary
The dielectric properties and reliability characteristics of NIS nitrided oxides are investigated in this chapter. An obvious oxidation rate retardation effect is observed for the nitrided oxides with nitrogen-implanted Si substrate. Dielectric property is strongly depended on NIS dosage and post-oxidation annealing temperature. NIS dosage less than 1×1014 cm-2 is helpless to oxidation rate suppression accompanying with degraded dielectric reliability. On the contrary, the samples with 1×1015 cm-2 NIS not only can use to grow multiple oxide thickness to meet SOC requirement, but also improve stress immunity apparently. Nitrogen implantation also generates a uniform distribution nitrogen profile in the dielectric bulk, which can be used as an effective diffusion barrier to resist boron penetration. NIS nitrided oxides could effectively suppress trap generation and improve time-to-breakdown and charge-to-breakdown, also suitable to reduce process steps of the SOC technology.
Table 3.1 Experimental conditions of nitrided gate oxides formed by pre-oxidation NIS and post-oxidation NO-annealing.
NIS dosage (cm-2) Anneal Gas TOX (Å)
0 1 × 1013 1 × 1014 1 × 1015
30 √ √ √ √
22 √ √ √ √
NO anneal
19 √ N/A N/A N/A
30 √ √ √ √
22 √ √ √ √
N2 anneal
19 √ N/A N/A N/A
Table 3.2 Flat-band voltages and interface state densities of NO- and N2-annealed NIS nitrided oxides.
VFB
NIS NO-GOX (V) N2-GOX (V) ∆VFB (mV)
0 -1.085 -1.055 -30
1 × 1013 cm-2 -0.992 -0.958 -34 1 × 1014 cm-2 -0.925 -0.896 -29 1 × 1015 cm-2 -0.825 -0.816 -9 Dit
NIS NO-GOX (V) N2-GOX (V) ∆Dit (cm-2 eV-1) 0 7.06×1011 4.88×1011 2.18×1011 1 × 1013 cm-2 8.82×1011 4.93×1011 3.89×1011 1 × 1014 cm-2 9.11×1011 5.11×1011 4.00×1011 1 × 1015 cm-2 2.45×1012 1.90×1012 5.50×1011
Table 3.3 Thickness and dielectric constant variation for NO- and N2-annealed NIS nitrided oxides.
NIS Dosage QMCV TEM κ
0 26.3Å 27.3Å 4.01
1 × 1013 cm-2 27.3Å 27.6Å 3.94
1 × 1014 cm-2 26.6Å 27.2Å 3.99
N2 anneal
1 × 1015 cm-2 20.2Å 23.3Å 4.50
0 24.9Å 25.8Å 4.20
1 × 1013 cm-2 25.7Å 27.2Å 4.13
1 × 1014 cm-2 25.2Å 26.8Å 4.15
NO anneal
1 × 1015 cm-2 19.7Å 23.2Å 4.60
-2.0 -1.5 -1.0 -0.5 0.0 0.5
14 N2-annealed NIS nitrided oxides
Capacitance ( pF )
14 NO-annealed NIS nitrided oxides
Capacitance ( pF )
Fig. 3.1 Plots of high frequency C-V curves of 22Å (a) N2-annealed (b) NO-annealed NIS nitrided oxides. Significant oxidation rate retardation is inspected as NIS dosage larger than 1×1014 cm-2. As NIS dosage larger than 1×1015 cm-2, clear VFB shift and Dit increment is observed.
18
Open : N2-annealing Close : NO-annealing
NIS Implantation Dosage ( cm-2 ) QMCV
NIS Implantation Dosage ( cm-2 ) N2-annealing
NO-annealing
(b)
Fig. 3.2 (a) Oxide thickness (b) dielectric constant as a function of nitrogen dosage implanted into the silicon substrate before oxidation. Dielectric constant increases from 3.9 to 4.6 for NO-annealed NIS nitrided oxides with heavy implantation dosage.
0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0
N2-annealed NIS nitrided oxides
Leakage Current Density ( A / cm2 )
Gate Voltage ( V )
Leakage Current Density ( A / cm2 )
Gate Voltage ( V )
Fig. 3.3 Direct tunneling leakage current density as a function of gate voltages of 22Å (a) N2-annealed (b) NO-annealed NIS nitrided oxides. Direct tunneling leakage current density is strongly dependent on the dosage of nitrogen implanted into Si substrate..
(a)
Nitrogen Concentration ( cm-3 )
Depth ( A ) w/o NIS
1014 NIS 1015 NIS
(b)
Fig. 3.4 (a) XPS depth profiles of 22Å NO-annealed nitrided oxides with 4×1015 cm-2 NIS. Evidence of Si3N4-like interface is observed. (b) SIMS nitrogen depth profiles of 30Å NO-annealed NIS nitrided oxides. NIS incorporates uniform nitrogen distribution in the bulk. Atomic Concentration (%) O 1 s
N 1 s NO-annealed NIS nitrided oxides NIS = 4×1015 cm-2
0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0
N2-annealed NIS nitrided oxides CVS, -4V, 100sec
Leakage Current Density ( A / cm2 )
Gate Voltage ( V )
Leakage Current Density ( A / cm2 )
Gate Voltage ( V )
Fig. 3.5 SILC characteristics of 22Å (a) N2-annealed (b) NO-annealed NIS nitrided oxides at -4V CVS for 100sec. Maximum current increase after CVS occurs near flat band region. Increased SILC is negligible for 1×1015 cm-2 NIS nitrided oxides.
0 20 40 60 80 100
Stressing Time ( sec ) (a)
Maximum Trap Generation Rate ( % )
Injected Charges ( C / cm2 ) (b)
Fig. 3.6 (a) Transient hole-trapping behaviors (b) maximum trap generation rates of 22Å NO-annealed NIS nitrided oxides at -20 mA/cm2 constant current stress. NIS nitrided oxides with 1×1015 cm-2 dosage has negligible trap generation rate for both CVS and CCS.
1 10 100 1000 10000 -3
-2 -1 0 1 2 3
TDDB Weibull plots ( CVS -4.3V ) NO-annealed NIS nitrided oxides
ln ( -ln ( 1-F ) )
Time ( sec ) w/o NIS
1013 NIS 1014 NIS 1015 NIS
(a)
2.0 2.5 3.0 3.5 4.0
w/o NIS 1013 1014 1015 TDDB Weibull plots ( CVS -4.3V )
NO-annealed NIS nitrided oxides
Weibull Slope
NIS Implantation Dosage ( cm-2 ) (b)
Fig. 3.7 (a) tBD Weibull distribution (b) Weibull slopes of 22Å NO-annealed NIS nitrided oxides under -4.3V constant voltage stress. The reliability of NIS nitrided oxides is substantially relied on NIS dosage, tBD and Weibull slope are increased only for NIS nitrided oxides with 1×1015 cm-2 dosage.
Fig. 3.8 The HRTEM cross-sectional images of 22Å N2-annealed NIS nitrided oxides.
(a) without NIS (b) 1013 cm-2 (c) 1014 cm-2 (d) 1015 cm-2. Sample with 1015 cm-2 NIS not only smoothes interface but also reduces physical thickness.
n+-poly
27.3Å ± 2.3Å
p-Sub (a) Without NIS
5 nm
p-Sub n+-poly
27.6Å ± 3.5Å (b) 1013cm-2
5 nm
p-Sub n+-poly
27.2Å ± 2.7Å (c) 1014 cm-2
5 nm
(d) 1015cm-2
p-Sub n+-poly
23.3Å ± 1.3Å
5 nm
Fig. 3.9 The HRTEM cross-sectional images of 22Å NO-annealed NIS nitrided oxides.
(a) without NIS (b) 1013 cm-2 (c) 1014 cm-2 (d) 1015 cm-2. Sample with 1015 cm-2 NIS not only smoothes interface but also reduces physical thickness.
p-Sub n+-poly
27.2Å ± 3.1Å (b) 1013cm-2
5 nm
25.8Å ± 1.7Å n+-poly
p-Sub (a) Without NIS
5 nm
n+-poly
26.8Å ± 2.3Å
p-Sub (c) 1014 cm-2
5 nm
p-Sub n+-poly
23.2Å ± 1.3Å (d) 1015cm-2
5 nm
0.5 1.0 1.5 2.0 2.5
NO-annealed NIS nitrided oxides
w/o NIS 1013 1014 1015
RMS Surface Roughness ( A )
NIS Implantation Dose ( cm-2 )
Fig. 3.10 Substrate surface roughness of NO-annealed NIS nitrided oxides after dielectrics removal by diluted HF solution. Evidence of smooth interface is revealed for samples with 1015 cm-2 NIS and post-oxidation NO annealing.
CHAPTER 4
Simulated Characteristics of Stacked-Gate Flash Memories with Inter-Poly High-κ Dielectrics
4.1 Introduction
In pursuing the high speed and low power operation of flash memory technologies, the employment of high-permittivity (κ) inter-poly dielectrics (IPDs) into flash memories has attracted much attention recently [21]-[23]. By increasing the floating gate coupling ratio, high-κ IPDs can lead to a high electric field across tunnel oxide even at very low control gate voltage. To successfully employ high-κ IPDs in flash memory, one must take charge retention issues into consideration and make sure that the barrier height (ϕB) between Si and the new adopted high-κ dielectrics should be larger than 1.5eV for effectively suppressing the loss of floating gate charges through electron thermal emission [33]. Usually, dielectrics with higher κ inherently have lower ϕB. Therefore a trade-off between dielectric constant and barrier height is inevitably required in trying to implement the high-κ dielectrics in flash memories.
Recently, aluminum oxide (Al2O3) [17], [44]-[46] and hafnium oxide (HfO2) [20], [47]-[50] had been proved as promising candidates for the gate dielectrics of sub-0.1 µm device due to their higher dielectric constant (κ), relatively high ϕB and superior thermal stability. Nonetheless, the effects of these kinds of high-κ dielectrics on flash memories are seldom investigated. In this chapter, the effects of Al2O3 and
HfO2 serving as the IPD of flash memories were studied with different programming and erasing schemes through 2-D MEDICI simulator. We found that dielectric with medium κ value is the most promising IPD candidate because the gate coupling ratio would be rapidly saturated as κ is greater than 25. It is also demonstrated that the improvement of high-κ IPDs is more effective with Fowler-Nordheim (FN) injected programming and erasing than hot electron (HE) injection. As a result, high-κ IPDs are suitable for next generation NAND-type stacked-gate flash memories.
4.2 Simulation Details
To examine the impact of high-κ IPDs, simulations are carried out using the conventional stacked-gate flash cell with SiO2 tunnel oxide (TOX). Two-dimensional MEDICI [83] simulator is employed for the performance simulations of a 0.45µm stacked-gate n-channel flash memory with several kinds of high dielectric constant IPD. They are Al2O3 and HfO2. The barrier heights of Al2O3 and HfO2 are extracted from [84], which are 2.8eV and 1.5eV, respectively. The permittivity is 9 for Al2O3 and 25 for HfO2, which are referred from [85]. The TOX thickness is 100Å.
Equivalent oxide thickness (EOT) of oxide-nitride-oxide (ONO) and the physical thickness of other two high-κ IPDs are defined as 140Å. Dielectric parameters of various IPDs are listed in Table 4.1. For comparison, programming of the devices is achieved either by channel-hot-electron injection (CHE) or channel-Fowler-Nordheim injection (CFN). All of the devices are erased by the source-side Fowler-Nordheim (SFN) ejection from the floating gate (FG), by assuming 1×10-13 C/µm charges pre-existed in FG. In order to enhance the efficiency of SFN ejection, deeper source junction than drain junction is formed. Cross-sectional view of simulated device
structure is shown in Fig. 4.1. The programming and erasing time is defined as the shift of device threshold voltage (VTH) reaches 3 volts during measurement. After extracting from MEDICI simulator, Al2O3 and HfO2 IPD can increase the gate coupling ration by 45% and 92%, respectively, which can be used to scale down the operation voltage effectively.
4.3 Results and Discussions
According to International Technology Roadmap for Semiconductor (ITRS) criteria, the required IPD thickness for NOR- and NAND-type flash memories is 10-13 nm for next year [28]. However, thickness scaling of ONO IPD using current thermal and/or CVD oxynitride technologies is not sufficient to meet the stringent data retention requirement due to the unavoidable leakage current [30], [32].
Therefore, there is a strong demand to incorporate alternative high-κ dielectrics on nonvolatile memories for enhancing performance while suppressing charge loss.
4.3.1 Basic Characteristics of Flash Memories with High-κ IPDs and SiO2 TOX
Figure 4.2(a) compares the erased state IPD electric field, defined as IPD voltage/140Å physical thickness, of stacked-gate flash memories as a function of control gate voltage (VGS). The IPD electric field tends to decrease rapidly as κ increases. Since the large IPD electric field across on the erased-state cells will result in more severe charge loss from floating gate to control gate, the flash memories with ONO IPD are expected to possess small programming window than high-κ IPDs. The flash memories with ONO IPD also reduce the electric field on the TOX, as shown in
Fig. 4.2(b). For device performance consideration, flash memories should be fabricated with small IPD electric field and large TOX electric field to obtain superior charge retention and high program/erase (P/E) speed simultaneously. Conventional ONO IPD is charge leaky and hard to P/E, which can not meet the stringent charge retention and flash P/E requirement. Fortunately, flash memories with high-κ IPDs can couple large amount of control gate bias to the floating gate, exhibit small IPD electric field as well as large TOX electric field, which are prone to retain charges and to scale down applied voltages.
The linear region and saturation region transfer characteristics (IDS-VGS) of the stacked-gate flash memories with high-κ IPDs and SiO2 TOX are displayed in Fig. 4.3.
The flash memories with ONO IPD exhibits larger subthreshold swing (SS) and significant off-state current, especially for higher drain biases, which are caused by inevitable drain turn-on. It is known drain turn-on is proportional to the drain coupling ratio (αD) and inversely proportional to the gate coupling ratio (αG), which are defined as below [86].
Drain coupling ratio (GCR)
Total D
D C
= C
α (4-2)
Gate coupling ratio (DCR)
Total gate transistor can go into depletion-mode operation and can conduct current even when VGS < VTH. Moreover, drain current of stacked-gate flash memories is also controlled by αG and capacitive coupling ratio f, not as simple as conventional
MOSFET. The relation between IDS and VGS is given by:
Saturation region ( )
2
voltage through large f, and drive-in current be strongly dependent on the drain voltage, namely drain turn-on phenomenon. With increasing the permittivity of high-κ IPD, both SS and drive current are improved due to higher αG and higher gate controllability. However, large αG will increase electric filed on the tunnel dielectrics and enhance gate-induced drain leakage (GIDL).
Figure 4.4 indicates the output characteristics of the stacked-gate flash memories with high-κ IPDs and SiO2 TOX. Thanks to higher gate coupling, flash memories with high-κ IPDs not only exhibit higher drive-in current than conventional ONO IPD, but also suppress the drain turn-on. Figure 4.5 exhibits the substrate current of flash memories with high-κ IPDs and SiO2 TOX. Equivalent maximum substrate current is obtained regardless of the κ-value of the IPDs. The maximum channel electric field is determined by the voltage difference between VGS and VDsat, which is defined as the drain voltage when pinch-off occurs, and expressed by:
Channel electric field Emax ∝ VDS − VDsat (4-6) For high-κ IPDs, the channel electric field is suppressed by high gate coupling ratio and generates less impact ionization near drain junction. Since the substrate current is
proportional to the IDS and impact ionization rate, high drain current of high-κ IPDs will be compensated by less impact ionization. Consequently, equivalent substrate current is expected regardless of the κ-value of the IPDs.
4.3.2 Program/Erase Characteristics of Flash Memories with High-κ IPDs and SiO2 TOX
The CHE current injected to FG of stacked-gate flash memories with high-κ IPDs and SiO2 TOX is compared in Fig. 4.6(a). Although high-κ IPDs exhibit higher CHE current injection to the FG, the contribution of high-κ IPDs seems unobvious.
Figure 4.6(b) calculated CHE injection efficiency, defined as CHE current injected to FG/IDS, similarly unapparent improvement is observed. Merely 2 times improvement of CHE injection efficiency is obtained by changing ONO IPD to high-κ IPDs. Since VTH shift after programming is controlled by injected charges/CIPD, only slightly improvement of programming speed is expected with CHE injection. The CHE programming times as a function of VGS for various IPDs are shown in Fig. 4.7. For the 10 µs programming time, the control gate voltage can be reduced by 16% and 11% with replacing ONO IPD by Al2O3 and HfO2 IPD, respectively. Noteworthy, the improvement of high-κ IPDs disappears at larger control gate voltage.
Figure 4.8 compares the FN tunneling current injected to FG under CFN programming schemes of stacked-gate flash memories with high-κ IPDs and SiO2
TOX. Injected FN current reveals a stronger dependence on the permittivity of the IPDs than HE current. Larger than 80 times FN current increased is observed while replacing ONO IPD to high-κ IPDs. Figure 4.9 shows the relationships between CFN programming time and VGS for flash memories with different IPDs. Obviously, the
programming speed of CFN can be significantly improved using high-κ IPDs. Al2O3
can enhance programming speed by one order of magnitude and HfO2 can improve even further by two orders of magnitude. For the 10 µs programming time, 28% and 51% of VGS reduction can be achieved by changing ONO IPD with Al2O3 and HfO2
IPD, respectively. Compared to the results in Fig. 4.7, the benefit of employing high-κ IPDs is obviously more effective in CFN programming than CHE programming. This is ascribed to that FN tunneling current is exponentially dependent on the electric field, the larger electric field on TOX coupled through high-κ dielectrics, thus, is more efficient in electron injection [21]. On the other hand, CHE injection is controlled by both the electric field on TOX and impact ionization rate. Higher injection efficiency resulting from the higher vertical electric field on TOX will be compensated by the decreasing impact ionization rate, as seen in Fig. 4.5. Therefore, the improvement of CHE programming in operation speed with high-κ IPDs is not as remarkable as that of CFN programming.
Figure 4.10(a) compares the programmed state IPD electric field of the stacked-gate flash memories as a function of VGS with floating drain and substrate.
The programmed state has small negative electric field (electrons tunneling to control
The programmed state has small negative electric field (electrons tunneling to control