Program/Erase Characteristics of Flash Memories with High-κ IPDs and

Chapter 4 Simulated Characteristics of Stacked-gate Flash Memories

4.2 Simulation Details

4.3.2 Program/Erase Characteristics of Flash Memories with High-κ IPDs and

The CHE current injected to FG of stacked-gate flash memories with high-κ IPDs and SiO2 TOX is compared in Fig. 4.6(a). Although high-κ IPDs exhibit higher CHE current injection to the FG, the contribution of high-κ IPDs seems unobvious.

Figure 4.6(b) calculated CHE injection efficiency, defined as CHE current injected to FG/IDS, similarly unapparent improvement is observed. Merely 2 times improvement of CHE injection efficiency is obtained by changing ONO IPD to high-κ IPDs. Since VTH shift after programming is controlled by injected charges/CIPD, only slightly improvement of programming speed is expected with CHE injection. The CHE programming times as a function of VGS for various IPDs are shown in Fig. 4.7. For the 10 µs programming time, the control gate voltage can be reduced by 16% and 11% with replacing ONO IPD by Al2O3 and HfO2 IPD, respectively. Noteworthy, the improvement of high-κ IPDs disappears at larger control gate voltage.

Figure 4.8 compares the FN tunneling current injected to FG under CFN programming schemes of stacked-gate flash memories with high-κ IPDs and SiO2

TOX. Injected FN current reveals a stronger dependence on the permittivity of the IPDs than HE current. Larger than 80 times FN current increased is observed while replacing ONO IPD to high-κ IPDs. Figure 4.9 shows the relationships between CFN programming time and VGS for flash memories with different IPDs. Obviously, the

programming speed of CFN can be significantly improved using high-κ IPDs. Al2O3

can enhance programming speed by one order of magnitude and HfO2 can improve even further by two orders of magnitude. For the 10 µs programming time, 28% and 51% of VGS reduction can be achieved by changing ONO IPD with Al2O3 and HfO2

IPD, respectively. Compared to the results in Fig. 4.7, the benefit of employing high-κ IPDs is obviously more effective in CFN programming than CHE programming. This is ascribed to that FN tunneling current is exponentially dependent on the electric field, the larger electric field on TOX coupled through high-κ dielectrics, thus, is more efficient in electron injection [21]. On the other hand, CHE injection is controlled by both the electric field on TOX and impact ionization rate. Higher injection efficiency resulting from the higher vertical electric field on TOX will be compensated by the decreasing impact ionization rate, as seen in Fig. 4.5. Therefore, the improvement of CHE programming in operation speed with high-κ IPDs is not as remarkable as that of CFN programming.

Figure 4.10(a) compares the programmed state IPD electric field of the stacked-gate flash memories as a function of V_GS with floating drain and substrate.

The programmed state has small negative electric field (electrons tunneling to control gate) at zero V_G due to pre-existed negative charges in the FG, and then change to positive electric field (electrons tunneling from control gate) at high negative control gate bias. High positive IPD electric field will result in unwanted carrier injection from control gate to floating gate, flash memory with ONO IPD is expected to possess poor erase window than high-κ IPDs, especially for high voltage erasing. Flash memories with ONO IPD also reduce electric field on TOX and degrade erasing speeds, as shown in Fig. 4.10(b). The corresponding band diagrams of programmed state flash memories with high-κ IPDs and ONO IPD during erasing are shown in Fig.

4.11(a) and (b), respectively. For flash memories with high-κ IPDs, small negative electric field on IPD and large positive electric field on SiO2 TOX induced by high gate coupling ratio will enhance electron ejection from FG to control gate and source region simultaneously, which is expected to exhibit fast erasing speed and large erasing window. However, large positive electric field across on ONO IPD will degrade both erasing speed and erasing window due to unwanted electron injection from control gate to FG.

Figure 4.12 compares the FN tunneling current ejected from FG under SFN erasing schemes of stacked-gate flash memories with high-κ IPDs and SiO2 TOX.

Ejected FN current reveals a strong dependence on the permittivity of the IPDs.

Similar to CFN programming, larger than 80 times FN current increase is observed while replacing ONO IPD to high-κ IPDs during erase. SFN erasing time verse VG for memories with high-κ IPDs and SiO2 TOX is shown in Fig. 4.13. Employing high-κ dielectrics as the IPD can also tremendously improve erasing speed. Al₂O₃ and HfO₂ IPD can reduce erasing time by one and two order of magnitude, respectively. For the 0.1 ms erasing time, Al₂O₃ can reduce the erasing voltage by 31% while HfO₂ can further diminish erasing voltage by more than 48%. In summary, operation voltage reductions are listed in Table 4.2. Even though the improvement is more obvious in FN injection than HE injection, our simulation results clearly indicate stacked-gate flash memories with high-κ IPDs and SiO2 TOX can be used to replace both NAND- and NOR-type flash cells, in terms of control gate voltage reduction and operation speed promotion.

The improvement of P/E speed is found to be more significant between ONO IPD and Al2O3 IPD than between Al2O3 IPD and HfO2 IPD. In order to investigate the effect of dielectrics with higher κ value, an artificial dielectric with κ equal to 50 and

ϕB larger than 1.5eV is employed for comparison. The results in Fig. 4.2 - 4.13 show that only slightly improvement in P/E speed is observed when κ is changed from 25 to 50. Voltage reduction ratio will be rapidly saturated as κ becomes larger than 25.

Hence, it can be claimed that very high-κ dielectrics may not be an effective IPD candidates for stacked-gate flash memories even though they have a ϕB larger than 1.5eV.

4.4 Summary

In order to realize high speed and low power operation of flash memory technologies, devices with high coupling ratio are necessary. From MEDICI simulation, Al2O3 IPD and HfO2 IPD can increase gate-coupling ratio by 45% and 92%, respectively. By 2-D MEDICI simulation, flash memories with high-κ IPDs clearly exhibit significant improvement in programming/erasing speed over those with conventional ONO IPD. Moreover, it is found that high-κ IPDs are more effective for the memories programmed/erased with FN tunneling rather than channel hot carrier injection. Choosing HfO₂ as the IPD and using FN programming/erasing scheme, the operating voltage can be reduced 48% at a typical program time of 10 µs and 0.1 ms erasing time. Therefore, Al2O3 and HfO2 with medium high κ value and sufficient barrier height show the great potential for the application of high seed and low voltage flash memories. Our results also show that dielectrics with very high permittivity (κ >

25) may not be necessary for the IPD in stacked-gate flash memories. As a result, high-κ IPDs are suitable for next generation NAND-type stacked-gate flash memories.

Table 4.1 Dielectric constants and conduction band offsets with respect to Si of the IPD materials with fixed SiO2 TOX for simulated stacked-gate flash memories. * : physical thickness ~180Å, EOT ~ 140Å. ** : artificial high-κ material with sufficient κ-value and ∆E_C.

IPD Thickness κ ∆EC (ϕB)

ONO 140Å* ~ 5

Al₂O₃ 140Å 9 2.8

HfO2 140Å 25 1.5

κ = 50** 140Å 50 1.5

Table 4.2 Operation voltage reduction of stacked gate flash memories with high-κ IPDs and SiO2 TOX.

κ = 50 HfO2 Al2O3 ONO

GCR 0.895 0.814 0.615 0.424

DCR 0.016 0.029 0.067 0.112

SCR 0.041 0.076 0.171 0.266

GCR Improvement 110.91% 91.87% 44.98%

DCR Improvement 85.68% 73.77% 39.75%

SCR Improvement 84.56% 71.56% 35.56%

VGS 11.01 10.05 9.5 11.35

10µs CHE Program

Improvement 3.00% 11.45% 16.30%

VGS 6.89 7.65 11.41 15.88

10µs CFN Program

Improvement 56.61% 51.83% 28.15%

VGS -5.74 -6.23 -8.2 -12.04

0.1ms SFN Erase

Improvement 52.33% 48.20% 31.83%

(a)

(b)

Fig. 4.1 (a) Simulated 0.45µm n-channel device structure (b) equivalent electrical model of stacked-gate flash memories with several high-κ IPDs and TDs. Asymmetry source/drain junction for enhanced source-side erasing efficiency. Programming by either CHE or CFN injection; erasing by SFN erasing.

n⁺ Control Gate

High-κ TD

p-type Si n⁺

High-κ IPD

n⁺ G

S D

n⁺ Floating Gate

CIPD

CTD

S B D

0 2 4 6 8 10 12 14 16 18 20

Fig. 4.2 (a) IPD (b) TOX electric field as a function of control gate voltages of erased state stacked-gate flash memories with high-κ IPDs and SiO₂ TOX under V_D = V_B = V_S = -9.0V. High-κ IPDs can reduce IPD electric field as well as enhance TOX electric field.

0.0 0.5 1.0 1.5 2.0

Fig. 4.3 (a) Linear region (b) saturation region transfer characteristics of stacked-gate flash memories with high-κ IPDs and SiO₂ TOX. High-κ IPDs can increase drive-in current as well as enhance gate control ability, especially at high drain voltage.

0 1 2 3 4 5

Fig. 4.4 Output characteristics of stacked-gate flash memories with high-κ IPDs and SiO2 TOX at (VGS - VTH) = 10V.

Fig. 4.5 Substrate current of stacked-gate flash memories with high-κ IPDs and SiO₂ TOX. Maximum substrate current is independent of the κ-values.

0 2 4 6 8 10 12 14 16 18 20

Fig. 4.6 (a) CHE current injected to FG (IFG) (b) CHE injection efficiency (defined as IFG/IDS) as a function of control gate voltages of stacked-gate flash memories with high-κ IPDs and SiO₂ TOX. High-κ IPDs slightly enhance injection efficiency than ONO IPD, but not significantly.

0 2 4 6 8 10 12 14 16 18 20

CHE Programming Time ( sec )

VGS ( V )

Fig. 4.7 CHE programming time as a function of control gate voltages of stacked-gate flash memories with high-κ IPDs and SiO₂ TOX.

Fig. 4.8 CFN current injected to FG as a function of control gate voltages of stacked-gate flash memories with high-κ IPDs and SiO₂ TOX.

0 2 4 6 8 10 12 14 16 18 20 1E-10

1E-9 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 0.01 0.1 1 10 100 1000

High-κ IPD VD = V

B = V

S = -9.0 V

CFN Programming Time ( sec )

VGS ( V ) ONO

Al2O

HfO2

κ = 50

Fig. 4.9 CFN programming time as a function of control gate voltages of stacked-gate flash memories with high-κ IPDs and SiO₂ TOX. Significant improvement in CFN programming speed for high-κ IPDs is indicated.

0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20

Fig. 4.10 (a) Absolute IPD (b) TOX electric field as a function of control gate voltages of programmed state stacked-gate flash memories with high-κ IPDs and SiO₂ TOX under V_S = 5.0V. Drain and substrate terminals are floating. High-κ IPDs can reduce IPD electric field as well as enhance TOX electric field.

(a)

(b)

Fig. 4.11 Band diagrams of programmed state flash memories at the outset of erase for (a) high-κ IPDs and (b) ONO IPD.

Source FG

-High-κ IPD

SiO2

High-κ IPDs

Source FG

-ONO

IPD SiO₂

ONO IPD

0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20

Fig. 4.12 SFN current ejected from FG of stacked-gate flash memories with high-κ IPDs and SiO2 TOX under VS = 5.0V, floated drain and substrate terminal.

0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20

Fig. 4.13 SFN erasing time of stacked-gate flash memories with high-κ IPDs and SiO₂ TOX. High-κ IPDs crucially improve SFN erasing speed.

CHAPTER 5 Simulated Characteristics of Stacked-Gate Flash Memories with HfO

IPD and High-κ Tunnel Dielectrics

5.1 Introduction

In recognizing the high speed and low power operation of flash memory technologies, the employment of high-permittivity (κ) tunnel dielectrics (TDs) in flash memories has attracted much attention in order to reduce stress-induced reliability degradation in conventional SiO2 tunnel oxide (TOX) [28], [33]. The tunnel dielectric of flash memories has two roles. One is playing as a barrier to suppress charge leakage under ~3 MV/cm equivalent oxide field of read and retention. Hence, we need an appropriate barrier height and thickness. Second role is a charge transfer path. It must be robust enough under 10 MV/cm high field or 5V hot electron energy during charge injection mode, and both trapping and detrapping sites creation rates should be substantially suppressed. In order to avoid trap-assisted tunneling via one trap site, the minimum TOX thickness of conventional FG structure will be limit to 8 nm. This limits the tunnel SiO2 scaling and program/erase voltage reduction. Nitrided oxides have been intensively studied, but so far only 5 to 10 times improvement for low field leakage is achieved [33]. This is not enough, because it only achieves 1 nm reduction even with heavy nitridation.

Among various materials, both Ta₂O₅ and TiO₂ have narrow band gap resulting

in too low electron barrier height (ϕB) [84]. These films are not suitable from the viewpoint of flash reliability and thermally excited current. On the other hand, Si₃N₄, Al₂O₃, ZrO₂ and HfO₂ have reasonable bandgaps and barrier heights, these dielectrics are then the potential candidates [84]. In this chapter, the effects of high-κ materials Si3N4, Al2O3 and HfO2 serving as the TD of flash memories were studied with different programming and erasing schemes through 2-D MEDICI simulator. High-κ dielectrics served as the TD to replace SiO2 TOX can improve tunneling probability due to smaller ϕB. However, gate coupling ratio degrades as the dielectric constant of the TD increasing, which confines the high-κ TDs to be programmed and erased with hot-electron injection. Due to the contrary programming/erasing schemes compared to the high-κ IPDs, high-κ TDs are suitable for next decade NOR-type stacked-gate flash memories in terms of voltage reduction.

5.2 Simulation Details

To examine the impact of high-κ TDs, simulations are carried out using the conventional stacked-gate flash cell with fixed HfO2 IPD. Two-dimensional MEDICI [83] simulator is employed for the performance simulations of a 0.45µm stacked-gate n-channel flash memory with several kinds of high dielectric constant TD. They are Si₃N₄, Al₂O₃ and HfO₂. The barrier heights of Al₂O₃ and HfO₂ are extracted with the technique used in Ref. 84, which are 2.8eV and 1.5eV, respectively. The permittivity is 9 for Al₂O₃ and 25 for HfO₂, which are referred from Ref. 85. The physical thickness of HfO2 IPD and various tunnel dielectrics is 140Å and 100Å, respectively.

Dielectric parameters of various tunnel dielectrics are listed in Table 5.1. For comparison, programming of the devices is achieved either by channel-hot-electron

injection (CHE) or channel-Fowler-Nordheim injection (CFN). All of the devices are erased by the source-side Fowler-Nordheim (SFN) ejection from the floating gate (FG), by assuming 1×10^-13 C/µm charges pre-existed in FG. In order to enhance the efficiency of SFN ejection, deeper source junction than drain junction is formed.

Cross-sectional view of simulated device structure is the same with Fig. 4.1. The programming and erasing time is defined as the shift of device threshold voltage (VTH) reaches 3 volts during measurement.

5.3 Results and Discussions

According to International Technology Roadmap for Semiconductor (ITRS) criteria, the required TD thickness for NOR- and NAND-type flash memories is less than 7nm for next year [28]. However, thickness scaling of SiO2 tunneling oxide has been strongly limited by the unavoidable stress-induced leakage current caused by 1×10⁵ program/erase cycling [87], [88]. Therefore, there is a strong demand to incorporate alternative high-κ dielectrics on nonvolatile memories for enhancing performance while suppressing charge loss.

5.3.1 Basic Characteristics of Flash Memories with HfO2 IPD and High-κ TDs

Figure 5.1(a) compares the HfO₂-IPD electric field of stacked-gate flash memories as a function of control gate voltage (V_GS) with various high-κ TDs. Since larger IPD electric field across on erased-state cells will result in more severe charge loss from floating gate to control gate, the flash memories with high-κ TDs are expected to possess smaller programming window than SiO₂ TOX. The flash

memories with high-κ TDs also reduce the electric field on the TD, defined as TD voltage/100Å physical thickness, as shown in Fig. 5.1(b). Therefore, the flash memories with high-κ TDs will reduce capacitive coupling from control gate to floating gate, exhibit large IPD electric field as well as small TD electric field.

Linear and saturation region transfer characteristics of the stacked-gate flash memories with various high-κ TDs are shown in Fig. 5.2. The flash memories with high-κ TDs not only depict the degraded subthreshold swing but also exhibit significantly large off-state current, especially for high drain bias, which are caused by the inevitable drain turn-on and the reduced gate coupling ratio. As the permittivity of tunnel dielectrics increases, more amount of drain voltage is coupled to floating gate, and deteriorates control gate controllability. Figure 5.3 indicates the output characteristics of stacked-gate flash memories with high-κ TDs. Albeit the high-κ TDs increase the drive current, remarkable drain turn-on are also observed. Figure 5.4 exhibits the substrate current of the flash memories with HfO2 IPD and high-κ TDs.

Referring to eq. (4-6) and (4-7), the maximum channel electric field of the high-κ TDs is larger than SiO2 TOX due to reduced gate coupling. Consequently, the high-κ TDs will increase drain current as well as enhance impact ionization, contributing to larger than 2 times maximum substrate current increment. This result clearly reveals that the high-κ TDs can increase hot electron injection and the improvement in CHE programming can be predicted.

5.3.2 Program/Erase Characteristics of Flash Memories with HfO2 IPD and High-κ TDs

The CHE current injected to the FG of the stacked-gate flash memories with

HfO2 IPD and high-κ TDs is compared in Fig. 5.5(a). By replacing SiO2 TOX to high-κ tunnel dielectrics, the injected hot electron current from the substrate to the FG is obviously increased. Figure 5.5(b) shows the calculated CHE injection efficiency of the stacked-gate flash memories with HfO₂ IPD and high-κ TDs. Similarly, the enhanced injection efficiency is obtained by increasing the κ-value of the tunnel dielectrics. The CHE programming times as a function of VGS for various TDs are shown in Fig. 5.6. For the 10 µs programming time, the control gate voltage can be reduced by 16%, 18% and 27% with replacing SiO2 TOX to Si3N4, Al2O3 and HfO2

TD, respectively. Although the electric field on high-κ tunnel dielectrics is lower than SiO₂ TOX, enhanced impact ionization rate and lower ϕB contribute to higher CHE programming speed. As a result, the flash memories with HfO2 IPD and high-κ TDs are suitable to supplant presently tunneling oxide in NOR-type array architectures.

Figure 5.7 compares the FN tunneling current injected to FG under CFN programming schemes of the stacked-gate flash memories with HfO2 IPD and high-κ TDs. Injected FN current reveals a stronger dependence on the permittivity of the TDs than HE current. More than 10 times FN current reduction is observed while replacing tunneling oxide to high-κ TDs. Figure 5.8 shows the relationships between CFN programming time and V_GS for flash memories with different TDs. Obviously, the degradation of CFN programming speed can be ascribed to the reduced tunneling current from substrate into the FG. Compared to the results in Fig. 5.6, the benefit of employing high-κ TDs is obviously only effective in CHE programming rather than in CFN programming. This is ascribed to that FN tunneling current is exponentially dependent on the electric field, the smaller electric field on high-κ TDs reduces electron injection efficiency than SiO2 TOX. Therefore, the application of the high-κ TDs in the stacked-gate flash memories with CFN programming is unbeneficial,

contrary to the CHE programming.

Figure 5.9(a) compares the programmed state IPD electric field of the stacked-gate flash memories as a function of VGS with floating drain and substrate.

Increasing the κ-value of the TDs will lead to undesired IPD electric field increment, the high-κ TDs may deteriorate erase window through charge injection between the FG and the control gate. As seen in Fig. 5.9(b), the flash memories with high-κ TDs also reduce electric field on the TDs and degrade erasing speeds, similar to the CFN programming. Referring to Fig. 4.11, large positive electric field for flash memories with high-κ TDs will limit electron in the FG to be erased through tunnel dielectrics while enhance unwanted electron injection from control gate to FG. Consequently, flash memories with HfO₂ IPD and high-κ TDs are therefore expected to reduce erasing speed as well as narrow down erasing window. Figure 5.10 compares the FN tunneling current ejected from the FG under SFN erasing schemes of the stacked-gate flash memories with HfO2 IPD and high-κ TDs. Ejected FN current reveals a strong dependence on the permittivity of the TDs. Similar to the CFN programming, larger

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