Chapter 1 Introduction
1.3 Organization of the Dissertation
There are nine chapters in this dissertation. Chapter 1 shows the background and motivation for the application of the ultrathin nitrided oxides and high-κ dielectrics.
In Chapter 2, the reliabilities of sub-3nm nitrided oxides formed by NO-annealing are shown. In our study, N atomic concentration is shown to depend on the initial oxide thickness, i.e., concentration increases as oxide thickness decreases, which was desired for the improvement of dielectric reliability in the ultra-thin thickness region. NO-annealing can achieve better SILC immunity for both constant voltage and constant current stress. Moreover, NO-annealing also improves interface smoothness and results in tighter TDDB distribution.
In Chapter 3, the reliabilities of sub-3nm nitrided oxides formed by nitrogen-implanted silicon substrate (NIS) are investigated. NIS dosage less than 1×1014 cm-2 is helpless to oxidation rate suppression and degrades dielectric reliability simultaneously. On the contrary, samples with 1×1015 cm-2 NIS not only can use to grow multiple oxide thickness to meet SOC requirement, but also improve stress immunity apparently. Nitrogen implantation also generates a uniform distribution nitrogen profile in the dielectric bulk, which can be used as an effective diffusion barrier to resist boron penetration. In conclusion, both NO-annealed and NIS nitrided oxides can improve dielectric reliability and are suitable to replace traditional SiO2 at 0.13µm and beyond.
In Chapter 4, the program/erase performance of stacked-gate flash memory with high-κ IPDs and SiO2 TOX are compared to ONO IPD. From MEDICI simulation, Al2O3 IPD and HfO2 IPD can increase gate-coupling ratio by 45% and 92%,
respectively. By 2-D MEDICI simulation, flash memories with high-κ IPD clearly exhibit significant improvement in programming/erasing speed over those with conventional ONO IPD. Moreover, it is found that high-κ IPD is more effective for the memories programmed/erased with Fowler-Nordheim (FN) tunneling rather than channel hot carrier (CHE) injection. Choosing HfO2 as the IPD and using FN programming/erasing scheme, the operating voltage can be reduced 48% at a typical program time of 10 µs and 0.1 ms erasing time.
In Chapter 5, the program/erase performance of stacked-gate flash memory on the κ-value of tunnel dielectric are studied. The effect of high-κ TD is quite different with high-κ IPD. Due to the reduced gate coupling ratio, the programming/erasing speed of stacked-gate flash memories with high-κ TD by using FN tunneling is helpless in operation voltage reduction. On the other hand, the increased electric field on HfO2 IPD would produce excess charge loss and narrow the operation window between programmed and erased state. Although the electric field on high-κ tunnel dielectrics is lower than SiO2 TOX, enhanced impact ionization rate and lower electron barrier height contribute to higher CHE injection current and efficiency.
Consequently, high-κ TD is more effective for the memories programmed/erased with hot electron injection rather than FN tunneling. Due to the contrary improvement in programming/erasing schemes, high-κ IPD and TD is suitable for next-generation NAND and NOR type stacked-gate flash memories, respectively.
In Chapter 6, the effects of surface ammonia (NH3) nitridation on inter-poly characteristics of reactive-sputtered (RS) Al2O3 dielectrics are evaluated. With surface NH3 nitridation, the formation of an additional layer with lower dielectric constant during post-annealing process can be significantly suppressed and reduced, compared to that without nitridation treatment. Furthermore, the presence of a thin Si-N layer
can make post-deposition annealing more effective in eliminating traps existing in the as-deposited films. As a result, a smoother interface and smaller electron trapping rate can contribute to the drastically reduced leakage current, enhanced breakdown field and QBD of Al2O3 interpoly capacitors with surface NH3 nitridation for both polarities.
In Chapter 7, the effects of post-deposition annealing (PDA) temperature on inter-poly characteristics of RS Al2O3 dielectrics are examined. It was found that the electrical properties of Al2O3 IPD strongly depend upon the PDA temperature. 900°C annealing is the best condition for the Al2O3 IPD electrical characteristic in terms of leakage current, electron trapping rate and charge-to-breakdown. The XPS and AES analyses indicate that this consequence is closely related to the compositional changes and excess oxygen concentration when changing annealing temperature. The results apparently demonstrate Al2O3 IPD with surface nitridation and optimized PDA temperature can effectively reduce charge transfer between CG and FG, better retention and disturb characteristics are expected by replacing ONO IPD to Al2O3 IPD.
In Chapter 8, thickness scaling down and reliability promotion of next-decade suitable IPD are inspected. The results clearly indicates high-κ IPDs, regardless of deposition tools, exhibits high potential to replace TEOS IPD. Moreover, MOCVD deposition demonstrates significant reliability improvement compared to RS deposition. As thin as 5nm and 3nm EOT of MOCVD-deposited Al2O3 and HfO2 IPD is suitable to meet the requirement of 45nm and 32nm generation stacked-gate flash memories, respectively.
Finally, in Chapter 9, the conclusions are made and the recommendation describes the topics which can be further researched.
Table 1.1 Materials properties of high-κ dielectrics, Al2O3, ZrO2 and HfO2.
High-κ Dielectrics
Al2O3 ZrO2 HfO2
Bandgap (eV) 8.3 5.82 6.02
Barrier Height to Si (eV) 2.9 1.5 1.6 Dielectric Constant 9 ~ 25 ~ 25
Heat of Formation
(Kcal/mol) 399 261.9 271
∆G for Reduction (MOx + Si → M + SiOx)
63.4 42.3 47.6
Thermal expansion coefficient (10-6oK-1)
6.7 7.01 5.3
Lattice Constant (Å) (5.43 Å for Si)
4.7 - 5.2 5.1 5.11
Oxygen Diffusivity
at 950oC (cm2/sec) 5×10-25 1×10-12
Fig. 1.1 Scaling limits of various gate dielectrics as a function of the technology specifications for low stand-by power technologies [Ref. 7].
Fig. 1.2 Leakage current density and EOT projection of nitrided oxides from ITRS roadmap 2003.
CHAPTER 2
Characteristics and Reliabilities of Sub-3nm High Temperature NO-Annealed Nitrided Oxides
2.1 Introduction
In order for a MOSFET to behave as a transistor, the gate must exert greater control over the channel than the drain does, i.e., the gate to channel capacitance must be larger than the drain to channel capacitance. A simple model suggests
Lmin α Tox × X1j/3 (2-1)
The scaling limit of Tox is therefore of paramount importance. Besides suppressing the short channel effect, reducing Tox improves drive current and generally but not always raises circuit speed.
The continuous shrinkage of device dimensions below a quarter-micron requires highly reliable ultra-thin dielectric films. In this thickness range, not only breakdown but also wearout of dielectric films is one of the key technological issues. As an alternative gate dielectric, nitrided oxides have drawn considerable attention due to their superior performance and reliability properties over conventional SiO2 [12]-[14], [51]-[56]. On possible approach to form nitrided oxides was post-oxidation annealing, including ammonia (NH3), nitrous oxide (N2O) and nitric oxide (NO) annealing. NH3
annealing will incorporate too large amount nitrogen into the gate oxide to reduce
carrier mobility, but simultaneously incorporate large amount of hydrogen into which will degrade hot carrier immunity [51]-[53]. N2O-annealing is another candidate for nitrogen incorporation, but requires a much higher thermal budget for sufficient nitrogen incorporation [12], [13], [54]. As a result, NO-annealing of an initial oxide is preferred to prepare nitrided oxide with sufficient concentration in a reasonable thermal cycle, considering the self-limiting nature of the growth proves in an NO ambient [13], [14], [55], [56].
In this chapter, characteristics and reliabilities of NO-annealed nitrided oxides are studied. Although NO-annealing will induce significant flat-band voltage shift and increase of the interface state density due to the pile-up of nitrogen near the interface, incorporation of nitrogen still can effectively suppress trap generation and improve time-to-breakdown and charge-to-breakdown.
2.2 Experiment Details
LOCOS isolated MOS capacitors were fabricated on p-type (100) silicon wafers.
After forming LOCOS isolation, wafers were cleaned and HF dipped before oxidation.
The gate dielectrics were grown at 750oC followed by either NO or N2 annealing at 850oC for an hour. Then 1500Å polysilicon was deposited with in-situ doped phosphorus of 2.5×1020 cm-3. Dopants were then activated at 950oC for 30sec. After gate electrodes patterned and contact holes etched, aluminum metallization was done followed by sintering at 450oC in N2 ambient.
Square or circular capacitors of different areas, ranging from 2.5×10-5 to 1×10-2 cm2, with LOCOS isolation are used to evaluate the gate oxide integrity. The physical
gate oxide thickness was determined by spectroscopic ellipsometer and compared with high-resolution transmission electron microscopy (HRTEM). The equivalent oxide thickness (EOT) was extracted by fitting the measured high-frequency capacitance-voltage (C-V) data from Hewlett-Packard (HP) 4284 LCR meter under an accumulation condition with quantum mechanical correction. The tunneling leakage current density-electric field (J-E) and the reliability characteristics of MOS capacitors were measured by semiconductor parameter analyzer HP4145A. Nitrogen depth profiles and compositions were analyzed by secondary ion mass spectroscopy (SIMS) and X-ray photoelectron spectroscopy (XPS). The micro-roughness of the wafer surface and the interface between nitrided oxides/silicon were detected by atomic force microscopy (AFM).
2.3 Results and Discussions
2.3.1 Accurate Models for Oxide Thickness Extraction
To meet the device requirement of the deep-submicron generation, the gate oxide thickness must be scaled down below 30Å. However, as oxide thickness scaled below 30Å, traditional C-V method is more and more difficult to extract the accurate oxide thickness due to large direct tunneling current and quantum confinement effect.
There are several reports used to extract the physical oxide thickness [57]-[61]. Oxide thickness extraction using different methods was summarized in Table 2.1.
2.3.1.1 Corrected Two-Frequency Method for High Leakage Dielectrics
Figure 2.1 shows C-V curves of 19Å NO-annealed GOX under 10kHz, 50kHz
and 100kHz measurement, a clear frequency dispersion was observed at the strong accumulation region due to series resistance ignoring [57]. Since capacitance is proportional to 1 2
f , higher measurement frequency will decrease oxide capacitance.
For example, 19Å NO-annealed GOX shows a 5% decrease in gate capacitance with 50kHz and 15% decrease with 100kHz, both comparing to 10kHz. The accurate model published by C.Hu [57] can eliminate this frequency-dependent capacitance measured at two different frequencies using (2-2) :
2 measured at the frequencyf2 , respectively. Inset also shows the C-V curves after modification, dispersion between three frequencies was disappeared. Unless stated otherwise, all C-V curves used in this report are the modified 50kHz-100kHz curve.
2.3.1.2 Quantum Confinement Effect Correction
As the channel length shrink, oxide thickness must be scaled to avoid severe short channel effect. However, when oxide thickness becomes thinner and the electric field becomes stronger, quantum confinement effect becomes more and more critical in the oxide thickness extraction. Quantum effect occurs when the vertical electric field is large enough to confine conduction carriers into the potential well at the surface, generates discrete band diagram. Since the capacitor structure was used in our experiments, only accumulation charge centroid is needed to be calculated. According
to [58], charge centroid at strong accumulation region (Xacc) can be calculated using
where T∆ is determined to be 6Å from quantum simulation using heavily doped silicon, Tphys is the physical oxide thickness, X2 = 10.8 for electrons and X2 = 13.5 for holes. VFB used in eq. (2-3) is roughly -1V since n+ polysilicon gate electrode and p-type substrate are used. After fitting C-V (calculated from 50kHz-100kHz C-V curve) with Xacc, Tphys (named QMCV) can be calculated as shown in Table 2.1.
Figure 2.2 compares the EOT and QMCV thickness extracted at VG = -2V of NO- and N2-annealed GOX. The difference can be calculated by the following expression:
NO-annealed GOX : ∆Tox = −0.03 TTEM +7.5 (Å) (2-4)
N2-annealed GOX : ∆Tox = −0.05 TTEM +8.1 (Å) (2-5)
where TTEM refers to the physical oxide thickness from HRTEM. The difference is about 7~8Å due to the quantum confinement effect. Otherwise, as oxide thickness decreases, the difference between EOT and QMCV will be more obvious since Xacc will contribute more significant portion in total oxide thickness. In addition, the model mentioned above is published for pure oxide, i.e., N2-annealed GOX in our experiment. It would be a little change in parameters fitting with nitrided oxide.
Furthermore, post-oxidation NO-annealing will incorporate additional nitrogen into GOX and slightly increase the dielectric constant (κ) from 4.0 to 4.2.
2.3.1.3 Extract Tox using Accumulation Direct-Tunneling Currents
As oxide thickness shrinkage down to the direct-tunneling region, tunneling current will strongly dependent on the oxide thickness [62]. For example, tunneling current will be increased by 10 times as oxide thickness decreases from 22Å to 20Å.
Therefore, using direct-tunneling current to extract oxide thickness becomes feasible solution. Since gate current in inversion mode is strongly dependent on the poly depletion effect (polysilicon doping concentration) and threshold shifts (substrate doping condition), using inversion gate current to determine oxide thickness becomes more difficult [59]. On the other hand, using accumulation gate current to determine oxide thickness is much easier since it will be independent on the poly depletion and the substrate condition. As a result, a simple model can be used to evaluate Tox from accumulation gate current at different gate bias, (named DTIV):
For VG = -1.5V :
where JG is the accumulation gate current density united A/cm2 and Tox united nm.
Figure 2.3 compares the physical oxide thickness extracting from QMCV and DTIV method with TEM thickness as the reference. As the oxide thickness thicker than 30Å, DTIV would become improper since the Fowler-Nordheim tunneling starts to contribute the leakage current, and the current dependence on oxide thickness becomes significantly weaker than direct-tunneling dominant region. Except for 30Å gate oxide, both the extracted QMCV and DTIV thicknesses reveal highly agreement with the TEM physical thickness.
2.3.2 Basic Characteristics of Sub-3nm NO-Annealed Nitrided Oxides
As shown in Table 2.1, NO-annealed GOX always had thinner EOT and QMCV thickness than N2-annealed GOX. Since NO-annealing will incorporate nitrogen into gate oxide and pile- up at SiO2/Si-sub interface [62]-[64], this will slightly increase the dielectric constant and result in thinner oxide thickness.
Figure 2.4 compares the magnitudes of direct tunneling current of both 19Å and 22Å N2- and NO-annealed GOX. The samples with NO-annealing do not introduce higher leakage current density than the control samples at higher electric field. In addition, small current peak can be observed in gate oxides due to traps assisted tunneling (TAT) at E < 1 MV/cm. After filling of the existed neutral traps with electrons, tunneling current will drop and return to the direct tunneling behavior.
Figure 2.5(a) compares the normalized C-V curves of N2- and NO-annealed GOX.
Slightly stretch-out and negative flat-band voltage shift (∆VFB) is observed for the samples with NO-annealing, which can be observed more clearly in Fig. 2.5(b).
Figure 2.6(a) shows XPS nitrogen distribution profiles of nitrided oxides after NO-annealing by XPS analyses. N is preferably piled up at the Si/dielectric interface with Si3≡N bonds [65], [66]. Due to lower electronegativity of N compared to O, N incorporation causes an increase in positive fixed charges and thereby, lowers the VFB. Moreover, nitridation also increases interface state densities due to Si3≡N bonding [62]. Figure 2.6(b) indicates the dependence between nitrogen peak concentration and initial oxide thickness. As the oxide thickness decreases, nitrogen will be incorporated more efficient because of less diffusion distance of NO gas [64]. Consequently, one can use the initial oxide thickness to control the peak nitrogen concentration at the same annealing condition. Moreover, as the oxide thickness less than 20Å, 850oC
significantly. As a result, reduced thermal budget is necessary for such ultra-thin gate oxide annealing from device performance point of view. Table 2.2 summarizes VFB
and Dit extracted from C-V curves and in-line Quantox non-contact C-V, respectively.
The results clearly indicate both ∆VFB and ∆Dit increases as decreasing initial oxide thickness, which is strongly affected by nitrogen concentration, under the same post-oxidation NO-annealing.
2.3.3 Reliability Characteristics of Sub-3nm NO-Annealed Nitrided Oxides
As the oxide thickness scales to the direct tunneling region, stress-induced leakage current (SILC) will become less and less significant because of insufficient energy of tunneling electrons, which will results in lower trap generation rate. In our experiment, all oxides had been measured using both constant voltage stress (CVS) and constant current stress (CCS). Figure 2.7 shows the J-V curves of 19Å gate oxides after -3.8V CVS for 100sec. The J-V curves of 22Å gate oxides after -4V CVS for 100sec is seen in Fig. 2.8(a). The most current increment after constant voltage stress occurs near -1V, i.e. flat-band voltage [67]. Since stress will generate extra interface state and bulk electron traps, leakage current will increase through tunneling via these traps. As the gate voltage increases from 0V to VFB, more and more amount of interface states are available for the electron tunneling from the gate after stress, thus more current increment is observed. As shown in the Fig. 2.7 and 2.8, both NO-annealed GOX have higher stress immunity than N2-annealed GOX which can be attributed to the formation of stronger Si3≡N bonds near the SiO2/Si-substrate interface [62]-[64], [68]. Figure 2.8(b) compares hole trapping rate during CVS. It should be reminded that as the oxide thickness thinner than 50~60Å, only hole trapping can be observed during stress [63], [64], [68]. During voltage stress, the gate
current monotonic increase over time clearly indicates that only the hole trapping is occurred. NO-annealed GOX can effectively suppress hole trapping rates during CVS.
For going into details about reliability phenomenon, Fig. 2.9 demonstrates maximum trap generation rates (Gtrap) under both CVS and CCS with various injection charges used to compare the oxide quality of 22Å N2-annealed and NO-annealed GOX. The relationship between Gtrap and injection charges are parabolic, SILC will increase more rapidly and then tends to saturate until breakdown occurs.
Regardless of constant voltage or current stress, NO-annealed GOX can effectively eliminate hole trapping generation compared to N2-annealed GOX due to stronger Si3≡N bonding, which is consistent with Fig. 2.8(b). Figure 2.10(a) compares the TDDB characteristics of 19Å and 22Å gate dielectrics stressed at -4.3V constant voltage stress. After Weibull plotting, NO-annealed GOX exhibits better tBD (time-to-breakdown) compared to N2-annealed GOX. The 63% accumulative failure rate for 19Å N2- and NO-annealed GOX are 149sec and 518sec, respectively.
NO-annealed GOX improves larger than 3 times of tBD than N2-annealed GOX. While increasing initial oxide thickness to 22Å, the 63% accumulative failure rate for NO- and N2-annealed GOX are 1600sec and 683sec, respectively. tBD improvement becomes smaller than thin oxide, but still larger than 2 times. QBD Weibull distribution of 22Å gate dielectrics stressed at -20 mA/cm2 constant current stress is shown in Fig.
2.10(b). The 63%-failure QBD for NO- and N2-annealed GOX are 42.4 C/cm2 and 16.1 C/cm2, respectively. NO-annealing not only improves QBD larger than 2 times but also results in larger Weibull distribution slope (β) under CCS, consistent with CVS results.
The HRTEM images of N2- and NO-annealed GOX, as seen in Fig. 2.11, reveal NO-annealing can help to smooth interface roughness and reduce interfacial layer (IL) thickness [69], as well as forming stronger Si3≡N bonding, we expect post-oxidation
NO-annealing will effectively improve dielectrics reliability characteristics.
Figure 2.12 compares β as function of dielectric thickness and stress voltage. β decreases with decreasing oxide thickness and increasing stress voltage [70]-[72]. In thin oxides, the conductive breakdown path consists of only a few traps and consequently there is a large statistical spread on the average density to form such a short path. In thick oxides, the breakdown path consists of a larger number of traps, and the spread on the trap density need to generate such a large path is smaller. This means that β as a function of oxide thickness is an intrinsic property of the degradation and breakdown mechanism. On the other hand, increasing stress voltage accelerates trap generation and has higher probability of forming conductive breakdown path. Moreover, NO-annealing also enhances β due to smoother interface and stronger Si3≡N interface bonding. Figure 2.13 predicts the 10-year lifetime using
Figure 2.12 compares β as function of dielectric thickness and stress voltage. β decreases with decreasing oxide thickness and increasing stress voltage [70]-[72]. In thin oxides, the conductive breakdown path consists of only a few traps and consequently there is a large statistical spread on the average density to form such a short path. In thick oxides, the breakdown path consists of a larger number of traps, and the spread on the trap density need to generate such a large path is smaller. This means that β as a function of oxide thickness is an intrinsic property of the degradation and breakdown mechanism. On the other hand, increasing stress voltage accelerates trap generation and has higher probability of forming conductive breakdown path. Moreover, NO-annealing also enhances β due to smoother interface and stronger Si3≡N interface bonding. Figure 2.13 predicts the 10-year lifetime using