Conclusions

According to SIA roadmap, oxide thickness small than 20Å is necessary for deep sub-quarter micron devices. However, pure SiO2 can’t meet the requirement due to the large tunneling current. In our study, N atomic concentration is shown to depend on the initial oxide thickness, i.e., with decreasing oxide thickness from 63Å to 22Å, the N concentration increases from 2.12 to 4.45 at.% in the interface, which was desired for the improvement of dielectric reliability in the ultrathin region.

NO-annealing can achieve better SILC immunity for both constant voltage and constant current stress. Moreover, NO-annealing also improves interface smoothness and results in tighter TDDB distribution. Even after process optimization in the future, NO-annealing can be used to improve device performance more apparent, as predicting in mind. As a result, NO-annealed nitrided oxides can improve dielectric reliability and are suitable to replace traditional SiO₂ at 0.13µm and beyond.

The dielectric properties and reliability characteristics of NIS nitrided oxides are also investigated. An obvious oxidation rate retardation effect is observed for nitrided oxides with nitrogen-implanted substrate. Dielectric property is strongly depended on NIS dosage and post-oxidation annealing temperature. NIS dosage less than 1×10¹⁴

-2

On the contrary, samples with 1×10¹⁵ cm^-2 NIS not only can use to grow multiple oxide thickness to meet SOC requirement, but also improve stress immunity apparently. Nitrogen implantation also generates a uniform distribution nitrogen profile in the dielectric bulk, which can be used as an effective diffusion barrier to resist boron penetration. NIS nitrided oxides could effectively suppress trap generation and improve time-to-breakdown and charge-to-breakdown, also suitable to reduce process steps of the SOC technology.

In order to realize high speed and low power operation of flash memory technologies, devices with high coupling ratio are necessary. From MEDICI simulation, Al₂O₃ IPD and HfO₂ IPD can increase gate-coupling ratio by 45% and 92%, respectively. By 2-D MEDICI simulation, flash memories with high-κ IPDs clearly exhibit significant improvement in programming/erasing speed over those with conventional ONO IPD. Moreover, it is found that high-κ IPDs is more effective for the memories programmed/erased with FN tunneling rather than channel hot carrier injection. Choosing HfO2 as the IPD and using FN programming/erasing scheme, the operating voltage can be reduced 48% at a typical program time of 10 µs and 0.1 ms erasing time. Therefore, Al₂O₃ and HfO₂ with medium high κ value and sufficient barrier height show the great potential for the application of high seed and low voltage flash memories. Our results also show that dielectrics with very high permittivity (κ >

25) may not be necessary for the IPD in stacked-gate flash memories.

On the other hand, the effect of high-κ TDs is quite different with high-κ IPDs.

Due to the reduced gate coupling ratio, the programming/erasing speed of stacked-gate flash memories with high-κ TDs by using FN tunneling is helpless in reduction operation voltage. On the other hand, the increased electric field on HfO2

IPD would produce excess charge loss and narrow the operation window between

programmed and erased state. Although the electric field on high-κ tunnel dielectrics is lower than SiO₂ tunnel oxide, enhanced impact ionization rate and lower ϕB

contribute to higher CHE injection current and efficiency. Consequently, high-κ TDs are only effective for the memories programmed/erased with hot electron injection rather than FN tunneling. Due to the contrary improvement in programming/erasing schemes, high-κ IPDs and TDs are suitable for next-generation NAND- and NOR-type stacked-gate flash memories, respectively.

Finally, the effect of NH₃ nitridation of Poly-I and PDA temperature on the electrical properties and reliability characteristics of the Al2O3 inter-poly capacitors are evaluated. With surface NH₃ nitridation, the formation of an additional layer with lower dielectric constant during post-annealing process can be significantly suppressed and reduced the EOT to 4.6nm, compared to that without nitridation treatment. Furthermore, the presence of a thin Si-N layer can make post-deposition annealing more effective in eliminating traps existing in the as-deposited films. As a result, a smoother interface and smaller electron trapping rate can contribute to the drastically reduced leakage current, enhanced breakdown field and Q_BD of Al₂O₃ interpoly capacitors with surface NH3 nitridation for both polarities. Moreover, it was found that the electrical properties of Al₂O₃ IPD strongly depend upon the PDA temperature. 900°C annealing is the best condition for the Al2O3 IPD electrical characteristic in terms of leakage current, electron trapping rate and charge-to-breakdown. The XPS and AES analyses indicate that this consequence is closely related to the compositional changes and excess oxygen concentration when changing annealing temperature. The results apparently demonstrate Al2O3 IPD with surface nitridation and optimized PDA temperature can effectively reduce charge transfer between CG and FG, better retention and disturb characteristics are expected

by replacing ONO IPD to Al₂O₃ IPD. MOCVD Al₂O₃ and HfO₂ IPD are investigated in order to further promote QBD of RS Al2O3 IPD. The QBD can be significantly improved as well as reduced leakage current density, enhanced breakdown voltage and effective breakdown field by using MOCVD replacing RS. As thin as 5nm and 3nm EOT of Al₂O₃ and HfO₂ IPD is suitable to meet the requirement of 45nm and 32nm generation stacked-gate flash memories, respectively.