Due to the increasing demand of low power consumption, high operation speed, mixed-type circuit integration and small-die-area for integrated circuit, scaling down using CMOS technology is increasingly becoming dominant. Along with this trend, the speed and power consumption of digital circuits have shown significant improvement.
However, designing analog circuits becomes difficult because of the drop in MOS intrinsic gain, increase in MOS leakage due to the thinning of the gate-oxide thickness, and decrease in the signal SNR, linearity, and device matching due to the reduction of supply voltage and MOS over-drive voltage. In order to overcome the above-mentioned problems, time-based or time-mode signal processing approach has been proposed [1].
By converting the voltage or current variables into corresponding time difference variables, signal processing in the analog domain is then transferred to processing in the
digital domain, where circuit design is more robust to PVT variations.
Roberts and Ali-Bakhshian [1] present a short review of time-to-digital and digital-to-time converters (TDCs and DTCs, respectively) adopting a time-mode signal processing perspective. Moreover, some mixed-mode circuits are used to convert non-time-domain signals to time-domain signals like input signals or output signals. In Fig. 1-1 (a), if the input is an analog voltage, it can be converted into a time-difference variable by a voltage-to-time converter (VTC). After the time-mode signal processing (TMSP) in the digital domain, the time-mode signal can be converted back to a voltage signal by a time-to-voltage converter (TVC). Here, the VTC and TVC are bridging circuits and the conversion process is very critical to ensure that the converted signal is reliable. Conversely, in Fig. 1-1 (b), if the input is a digital signal, it can be converted into a time difference variable as well by a DTC circuit. After some time-mode processing, it can be converted back into the original form using a TDC circuit. Similar to VTC and TVC, the TDC and DTC design are crucial to the whole system’s performance.
VTC TMSP
Figure 1-1 Time-Mode-Signal-Processing (TMSP) for processing analog and digital signals. (a) Voltage-in-voltage-out. (b) Digital-in-digital-out.
Due to the reasons described above, TMSP is becoming increasingly popular in several high-speed and moderate-accuracy analog circuits. For example, TDCs were used in all-digital phase-locked loops (ADPLLs) [2] and time-based analog-to-digital converters(ADCs) [3]－[6]. Again, a voltage-controlled oscillator (VCO) has been merged as a time-based quantizer in sigma-delta ADCs [7],[8]. It is a trend to convert an analog type signal to a time difference or a frequency difference signal, and then process the time domain signals using digital circuits. A growing number of published papers reporting such design in the time domain have demonstrated excellent performance compared to conventional designs in the voltage or current domain. Fig. 1-2 [7] shows a
VCO-based quantizer circuit and the relevant signal waveforms. The operation can be understood as follows. First, a ring oscillator converts a voltage signal Vtune to multi-phase clock outputs continuously. Next, the multi-phase clock signals are employed to trigger counters to start counting within a fixed clock period. After that, the counter outputs are summed and the results are saved to registers. The conversion is completed within a clock cycle and the counter is then reset before starting next conversion. If the output frequency of the ring oscillator is proportional to the input voltage Vtune, the analog voltage is successfully quantized to the relevant digital code in nature. A ring oscillator plus some digital counters and adders perform a
voltage-to-frequency conversion. The speed and accuracy of this quantizer take full advantage of modern CMOS processes since the ring oscillator’s gate delay and clock
phase spacing are reduced simultaneously with the process of scaling down. In addition, VCO-based quantizers can achieve first-order noise shaping of the quantization error.
Although the nonlinearity in the VCO’s transfer characteristic might seriously limit the resolution of VCO-based ADCs, sigma-delta feedback can be used to suppress the nonlinearity of the VCO quantizer. Consequently, VCO type quantizer has been widely adopted in continuous-time ΣΔ analog-to-digital converters. Fig. 1-3 is a proposed CT- sigma delta ADC. [7]
Figure 1-2 VCO employed as a quantizer [7]
Figure 1-3 The proposed CT-sigma delta ADC [7]
Another popular example of TMSP application is the all-digital PLL circuits employing TDC. Fig. 1-4 (a) shows a simplified block diagram of a charge pump based all-digital phase-locked loop (ADPLL) [9]. It consists of a phase-to-digital converter
(P2D), a digital loop filter, a digital controlled oscillator (DCO), and a feedback divider.
The P2D compares the phase difference between the reference clock FREF and the feedback clock FCKV, and converts it to a digital code. This digital code is filtered by the first-order digital low-pass filter (LF) and is then used to adjust the DCO’s phase or frequency. The P2D can be implemented as shown in Fig. 1-4 (b). It consists of a conventional phase/frequency detector (PFD) followed by a TDC. The PFD produces UP and DN pulses and the edge difference of UP and DN pulses is proportional to the phase error between the reference clock FREF and feedback clock FCKV. An L-bit TDC then digitizes the edge timing difference. The sign-bit of the TDC can also be generated according to the sampling results of the bottom D-flip flop. The operation of an ADPLL largely depends on the TDC resolution because it defines the resolution of PFD. A high-speed, high-accuracy TDC circuit (sub-gate delay resolution) design is often necessary in an ADPLL.
In Fig. 1-5, Lee et al. proposed a coarse-fine TDC design using an ADPLL [1]. It consists of an integer TDC and a sub-exponent TDC. The integer TDC is a conventional 5-bit TDC with one-bit resolution of two inverter delays. For the fractional time difference, a sub-exponent TDC to generate 1-of-n encoded 7b output with each bit representing a fraction 2-1,2-2,…,2-6,2-7 of the two inverter delay is used. The output of a
cascade of six stages of 2x time amplifiers (TAs) is tested by an integer checker. The
integer checker is a one-bit TDC and outputs ONE if the input time difference is larger than τ, which is equal to one bit resolution of the integer TDC.
(a)
(b)
Figure 1-4 All-digital phase-locked loop. (a) Block diagram. (b) A P2D converter. [9]
Figure 1-5 A coarse-fine TDC structure in all-digital phase-locked loop. [1]