The proposed time processing circuit specifications can be further improved to fit more accurate mixed-mode circuit design requirements. They are discussed as follows:
For the VTC circuit proposed in chapter 3, suggested to add an offset cancellation circuit in load-tuning circuit to improve the input dynamic range. Moreover, the mismatch of dual-delay lines also need to be taken into account if more accurate VTC design is needed. In addition to the mismatch effect, temperature variation also affect the transfer characteristic of VTC. Added an offset current that is proportional to the temperature variation in VREF generator circuit is good for temperature compensation.
At last, the comparator unit of the flash TDC also needs to be calibrated to ensure a
more accurate time delay between two RC-inverter paths of the comparator unit.
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Publication List
[1] Y.-C. Lin and H.-W. Tsao, ―A 5-bit 400-MS/s time domain flash ADC in 0.18µm CMOS,‖ Analog Integrated Circuits and Signal Processing (2020), pp. 369–378, Feb.
2020.
[2] Y.-C. Lin and H.-W. Tsao, ―A 10-Gb/s eye-opening monitor circuit for receiver
equalizer adaptations in 65-nm CMOS,‖ IEEE Trans. VLSI systems, vol. 28, no. 1, Jan.
2020, pp.23-34.
[3] Y.-C. Lin and H.-W. Tsao, ―A high-speed high-accuracy voltage-to-time difference converter for time domain anaolg-to-digital converters,‖ IEEE Int. Sym. on Circuits and Systems 2015 (ISCAS), pp. 2285–2288, May 2015.