The input voltage-mode signal is converted into a relative time-difference signal by the VTC in sequence. The next stage, a flash TDC, then quantizes the time-difference signal to the relevant digital code. Figure 3-16 shows the proposed flash TDC architecture. It is composed of several time comparing units (including delay cells and a D-flip-flop), a digital error-recovery circuit (for bubble error elimination), and code converters (1-of-n code to Gray code, Gray code to binary code).
Analogous to a conventional voltage-type flash ADC, the flash TDC contains numerous comparator units composed of delay cells and D-flip-flops. They are used to replace the reference voltage and comparators in the voltage mode flash ADC. In a conventional voltage mode flash ADC design, the compared voltage is typically generated from a resistor string. The static current consumption in the resistor string is usually substantial because of the need for high speed, accurate settling and high noise immunity. Moreover, the comparator circuit often requires a high speed and high gain preamplifier circuit at its front end for amplifying the noise level voltage difference before slicing it at the logic level. For high-speed operation, significant current consumption in the pre-amplifier circuit is inevitable.
However, in the present work, D-flip-flops are adopted to compare the time
difference in the flash TDC circuit. It is naturally digital and more robust than a conventional design in low-power-supply-voltage and noisy environment. Figure 3-17 (a) and (b) (c) contrast the comparator units of a flash ADC and a flash TDC.
Because the time resolution of the TDC is limited by the VTC intrinsic delay and the ADC sampling rate, one LSB delay in our design is roughly 25 picosecond in order to minimize the latency of VTC. The delay time is shorter than a gate delay in the 0.18-μm process. Structure in Fig. 3-17 (b) is not suitable for this design. Inverter pairs
with distinct RC delay elements are used to implement the delay differences Td1 and Td1+∆T shown in Fig. 3-17 (c). Given the superior matching properties of passive RC
elements, the required accuracy is not difficult to achieve. In our design, capacitances are fixed and resistances are variable. The total resistance value of two paths is constant in all comparison units, as shown in Figure 3-18.
-16D
Figure 3-16 Proposed Flash TDC architecture.
D Q
Figure 3-17 (a) Voltage domain flash ADC. (b)(c) Time domain flash TDC.
D Q D-flip-flops and active interpolation inverters.
In Figure 3-18, the polysilicon resistors Ri and Ri+1 have almost same layout area but different contact positions for varying their resistor values. The unit cell layout of resistors is to mitigate process variations. The design equation is given in Eq. (3.10).
Ri = R + i × ∆R, Ri+ = R − i × ∆R , i = 1 … 2n (if n bits ADC) (3.10)
Figure 3-19 shows simulation results of the delay difference property of an
inverter with an RC delay in TT, SS, and FF corner cases. Due to saving more power of
time comparators, the interpolation structure is adopted. The time resolution of comparator unit is 50 picosecond (±25picosecond).The delay range is 400 picosecond.
(=16×25 picosecond) . The simulations show that the range of ∆R is roughly equal to the resistor R value. The horizontal axis is the resistance value and the vertical axis is the delay difference between two delay lines. The simulation includes ±30% RC variation. Although such variation will result in ADC gain error and limit the ADC’s input dynamic range, this is not a very critical issue for ADC performance because it can be easy to calibrate [37].
Figure 3-19 The simulated delay difference characteristics of RC inverter delay-lines.
-600
For the flip-flop design, high-speed true single-phase clock (TSPC) D-flip-flops are adopted. In order to reduce the power consumption and chip area aggressively, an interpolation scheme in conventional flash ADC is also used. Half of the RC delay elements that could be eliminated. Figure 3-17 depicts a complete comparator unit with active interpolation inverters.
The gain error and offset of the VTC transfer characteristics will limit the whole ADC dynamic range notwithstanding any compensation circuit inside the VTC.
Extending the TDC input range is necessary to cover the PVT variation. In our design, two dummy comparator units are placed at the top and bottom of flash TDC. In addition, the bubble error in voltage-type flash ADC still occurs in the flash TDC if the layout of clock trace is not well matched. Comparing output of adjacent comparator unit results solves the bubble error problem. Furthermore, we convert the 1-of-n code to Gray code first. This facilitates reducing code transition errors resulting from the partial sampling effect of different D-flip flop due to their mismatch. The Gray code encoder is implemented using a ROM-based design.
3.5 Experimental Results
The 5-bit TADC prototype was fabricated in a 0.18-μm CMOS process. Figure 3-20 shows a photograph of the chip. The active area is 0.37 mm2 (including the VTC, TDC, and code converter).
Figure 3-20 Test Chip Die Photograph.
Figure 3-21 shows the chip test plan for the proposed ADC; some interface circuits are included on this chip. These include low-voltage differential signaling (LVDS) TX pairs for high-speed digital output signal integrity, LVDS RX for high-speed ADC clock input-signal integrity, and some bias circuits for LVDS TX/RX. The input analog signal
source is an RF signal generator. The clock source is a pulse pattern generator. Here, we implemented four copies of 5-bit flash TDCs for testing; these TADCs can be reconfigured as a 6-bit TADC with twice the data throughput rate in the future. In this prototype, however,only a 5-bit TADC is demonstrated.
Pattern nonlinearity (INL) results obtained using the sine-wave code density test method at 400 MS/s with an input frequency of 1 MHz. The peak DNL and INL are 1 and 1.7 LSB,
respectively. Figure 3-23 shows the measured spectrum at a 400-MHz sampling rate with an input at one fourth of the sampling rate; the SFDR and SNDR are 30.7 dB and 25.2 dB, respectively. The dynamic performance levels with respect to the input frequencies are shown in Figures 3-24 (a) and (b).
Figure 3-22 Measured (a) DNL and (b) INL results at fs=400 MHz, fin=1 MHz .
0 0.5 1 1.5 2
Figure 3-23 The measured output spectrum at fs=400 MHz, fin=100 MHz .
(a) (b)
Figure 3-24 The measured SFDR and SNDR V.S. input frequency at (a) fs=100 MHz (b) fs=400MHz.
Figure 3-25 Power breakdown of the prototype ADC.
The total power consumption of the ADC is 16 mW at 1.8V supply. Figure 3-25 shows the power breakdown. The major power consumers are the VTC and flash TDC.
The VTC consumes 17% of the total power because of high bandwidth requirements of the amplifier and buffer for delay-line bias regulated control. The flash TDC consumes 70% of the power of the ADC. The majority of the power is the dynamic current of the
VTDC
RC delay line in the comparison unit when delayed signals pass through it. Shrinking the inverters can reduce this significantly, but their sizes are limited by the device-matching consideration. The adoption of a more advanced process may effectively reduce the power consumption of the VTC and flash TDC.
Table 3-1 provides a performance summary of the prototype TADC. Table 3-2 shows a comparison with prior 0.18-μm CMOS high-speed ADCs with 3- to 7-bit resolution levels [38]—[43]. The figure of merit (FOM) is defined as following:
F = Po e (f⁄ s× 2 B) (3.11)
In table 3-3, the FOM results show that the power efficiency of the proposed TADC is sufficient and its performance is comparable to that of conventional voltage-type flash ADCs. Table 3-4 provides performance data of prior 4 to 8-bit high-speed-time-based ADC s for comparisons [44]—[47]. In [44], analog differential inputs are converted into two logic signals with a relevant time difference by two VTCs.
After that, a Vernier type TDC is used to transfer the time difference to the relevant digital code.In this design, the ADC resolution and operating speed are limited by the long delay time of the cascaded delay cells.In [47], the proposed TADC is based on a
remainder number system (RNS). It reduces the number of comparators and improves the power efficiency but the RNS system will exhibit an aliasing error if there is any impairment or noise in RNS quantizer. Sufficient numbers of quantization levels are therefore needed to minimize this error.
In [45] and [46], multiple VTCs are used in parallel to convert the input signal and the reference voltage simultaneously. The power consumption and input loading are doubled with the ADC resolution increased by every one bit. Moreover, the mismatch between these parallel VTCs needs to be calibrated [45] or averaged [46] by using auxiliary circuits. Compared to these time-based ADCs, the proposed VTDC only consumes less than 20% of total power. In other words, the majority of power consumption is due to digital circuits in the proposed TADC. It can be reduced significantly in case more advanced process is used.
Table 3-2 PERFORMANCE SUMMARY
SNDR(@fin=100MHz) 25.2 dB
ENOB(@fs=100MHz/400MHz) 4.01/3.89
FOM 2.69 pJ/conv.step
Table 3-3 PERFORMANCE COMPARISON (4-7 bits HIGH SPEED ADC IN 0.18 μm CMOS)
Ref. Architecture bits fs(GS/s) Power(mW) Calibration Area(mm2) FOM(pJ/Step)
[38] Flash 4 4 43 None 0.06 2.14
Ref. Technology bits fs(GS/s) Power(mW) Calibration Area(mm2) FOM(pJ/Step)
[44] 65 nm 4 5 34.6 Foreground 0.08 1
In this chapter, a novel TADC is proposed and the prototype has been implemented in a 0.18-μm CMOS process. By using a front-end VTC circuit, traditional voltage or