Ellermeyer et al. [50] proposed a 1D horizontal EOM (1D-HEOM) circuit. This 1D-HEOM provides an analog output voltage that is proportional to the horizontal eye-opening of the received data. In this design, a rectangular eye-mask with fixed height is selected to compare with the real data. The maximum allowed width of the eye mask, i.e., the eye traces that do not occur within the selected mask, is defined as the
horizontal eye-opening. The result of this is not always accurate because the horizontal eye-opening varies with different selections of the eye-mask height. In addition, the rectangular eye-mask cannot always fit the profile of a real eye diagram. Consequently, the EOM reports an inaccurate analog output voltage.
Analui et al. [53] tried to fit eye-masks to the real eye diagram by combining more rectangular eye-masks of different heights and widths. These eye-masks had the same mask error rate. Krishnan and Pavan [60] reconstructed the whole eye by splitting the eye diagram into many small pixels and calculating the probability that the input waveform lay within each pixel. All pixel probability densities were saved and then the entire eye diagram was plotted.
The true eye diagram can be plotted but requires a large amount of data to be calculated. This has a long computational time and cannot easily be applied for real-time equalizer adaptations.With a trade-off between speed and accuracy, the proposed EOM circuit attempts to calculate the probability density in two given horizontal pixel lines in order to evaluate the horizontal eye-opening of the received data for equalizer adaptations. The architecture of the proposed EOM is illustrated in Figure 4-1 (a). The concept is to calculate the probability density of the waveform occurring in every pixel of the central rows (the blue-colored pixels). The operation is
as follows. First, the input data is compared with the common-mode voltage and a voltage close to the common-mode voltage (e.g., y = 0 and y = ∆v). The comparison results are sampled by a fixed-phase clock (e.g., x = 1). After K data points are compared, the sampling clock is switched to the next phase (e.g., x = 2) and samples the next pixel. Their cumulative probability function (CDF) can be obtained by averaging the K points from the comparator. The difference between the CDFs at the two common-mode voltages (i.e., y = 0 and y = ∆v) is the probability density function (PDF) of the calculated pixel (i.e., x = 1). The PDF for the N pixels can be obtained step-by-step (i.e., x = 1, 2, … , N).
DAC
Figure 4-1 (a) The proposed 1D-EOM architecture. (b) The proposed 1D-EOM circuit block diagram.
· HEOM Meas. : Horizontal Eye Opening Measurment
In Figure 4-1, a voltage-to-time converter (VTC) and an n-bit digital-to-analog converter (DAC) are used to generate the multi-phase sampling clock for the comparators (i.e., x = 1, 2, … , N, N = 2n). The time resolution of the clock phase is the bit time over the total pixel number in the horizontal dimension.
The power and area overheads of the proposed EOM circuit are very small compared to those of a traditional EOM circuit with a bit-by-bit processing data structure. Table 4.2 compares the power, area and data rate of different type EOM circuits. The implementation of the proposed EOM circuit is shown in Figure 4-1 (b).
The differential inputs of the EOM are compared by comparators 1 and 2 simultaneously, and then the compared results are latched by the clock ck1 rising edge.
The threshold voltages of the two comparators are the alternative current (AC) ground and an approximate AC ground, respectively. The differential sampling clocks ck1 and ck1b are converted by a single-to-differential conversion block. The various phases of the sampling clock are generated by the VTC block. The sampling clock source CK1G is provided by the clock and data recovery circuit. In addition, a two-bit programmable delay line (PDL) circuit is inserted in front of the VTC. The purpose of the PDL is to adjust the initial horizontal sampling position of the eye diagram.
The delayed CK1G signal is used as a reference clock for the VTC. The purpose of the VTC is to generate a clock signal output with uniform phase spacing where the spacing is proportional to the control voltage VIN. Here, a six-bit sequential ramp-up DAC provides the control voltage for the VTC. It consists of a current-mode DAC and an up-counter. Initially, the up-counter is reset to zero and the DAC output voltage VIN
is set to its minimum. This forces the VTC output clock CKO to have the maximum delay time. After the first pixel calculation is completed, the up-counter ramps up and the DAC output VIN is incremented to reduce the VTC delay time pixel by pixel until all pixel calculations are finished. Due to the settling time requirement of the DAC, the VTC output clock CKO is valid only for half a cycle of the up-counter clock CKS.
During the other half of the cycle of CKS, the VTC output signal is disabled.
In Figure 4-1 (b), the synchronization signal CKEN provides a mask signal to enable the VTC output CKO. Therefore, there is half a cycle of the counter clock CKS for the DAC settling time requirement every time the up-counter value is changed. The two parameters, Idis and Vt, of the VTC are used to adjust its transfer gain and offset, respectively. Here, Idis is defined as the discharge current and Vt is the threshold voltage of the comparator inside the VTC. Section 4.3 will discuss the VTC operation in detail.
The comparator adopted in the proposed EOM circuit is a current-mode logic (CML) D-flip-flop, consisting of two CML latches. A detailed schematic is shown in Figure 4-2. In order to achieve a small difference in the threshold voltages of the two comparators, one of the comparators in the input differential pair has a slightly different size. Following these two comparators is a differential-to-single-end block. The purpose of this block is to convert the differential output into a single-end rail-to-rail signal. The
circuit implementation is shown in Figure 4-3. Some digital circuits, including counters, D-flip-flops, and XOR gates, are used to perform the CDF and PDF calculations. The calculated result is sent to the final stage to evaluate the size of the horizontal eye-opening. Finally, the proposed EOM circuit will provide a six-bit digital output signal HEO to express the size of the horizontal eye-opening.
VDD VDD
INP INN depicts the EOM input eye diagram. The input data rate is 10 Gbps and the channel loss is 5.4 dB. Figure 4-4 (b) displays the sampling clock, VTC DAC output, counter 1 output (CDF1), counter 2 output (CDF2), XOR gate output (PDF), and HEOM counter output (this value represents the horizontal eye-opening). Here, counter 1, counter 2, and the XOR gate are all ten bits and the HEOM output is six bits. The XOR gate output expresses the PDF of the horizontal pixels of the eye diagram, shown by waveform (5) in Figure 4-4 (b). It can be seen that data edge in some pixels occur if the pixels has large PDF values. The eye diagrams for different channel losses between 5 and 14 dB versus the 1D-HEOM simulation results are shown in Figure 4-5 and Figure 4-6 for
comparisons. Figure 4-4 (a) depicts the eye diagrams of the different EOM input data and Figure 4-4 (b) presents the corresponding PDF and the calculated HEOM results.
(a)
(b)
Figure 4-4 (a) EOM input eye diagram. (b) 1D-EOM related waveform.VTC output clock (for EOM sampling). (2) VTC DAC output. (3) Counter 1 output. (4) Counter 2 output. (5) XOR gate output. (6) HEOM<5:0> counter output results.
Figure 4-5 Input eye diagram VS. Different channel loss.
(1) Loss=5.4dB. (2) Loss=7.6dB. (3) Loss=9.5dB.
(4) Loss=11.1dB. (5) Loss=12.5dB. (6) Loss=13.7dB.
Loss=5.4dB HEOM=48
Loss=7.6dB HEOM=37
Loss=9.5dB HEOM=27
Loss=11.1dB HEOM=11
Loss=12.5dB HEOM=4
Loss=13.7dB HEOM=1
Figure 4-6 64 pixels PDF calculation results VS. Different channel model.