Low power and high resolution time-to-digital converters (TDCs) [14]－[16] have been widely used in mixed-signal circuits such as all-digital PLL (ADPLL) [17], time-domain analog-to-digital converters (ADCs) [18] － [21] and on-chip time measurement circuits [22]. To recognize a sub-gate delay time-difference signal, time-difference amplifier (TAMP) circuits have been developed in the front-ends of some TDCs to amplify a small time-difference signal. As shown in Figure 2-7, A TAMP can amplify a small time difference ∆Фin to ∆Фout, and ∆Фout is then fed into a LR-TDC (Low Resolution TDC) , it relaxes the resolution on TDC. Several type TAs are introduced in this section.
Figure 2-7 Time amplification relaxes resolution on TDC. [22]
2.3.1 SR-Latch-type Time-Difference Amplifiers [23]
Set/reset (SR)–latch-type time-difference amplifiers [23]－[25] operating in the metastable region can amplify a very small time-difference signal (of a picosecond or sub-picosecond scale) to a sufficiently large time-difference signal (of a scale of several picoseconds). The TA was designed to facilitate improvement of TDC resolution.
However, its linear range and metastable region are correlated.
The detailed circuit is presented in Figure 2-8 and relevant waveforms for inputs with small and large time-differences are presented in Figs. 2-9 (a) and (b), respectively.
As shown in Fig. 2-9 (a), for a small input time-difference of TD between INA and INB, the delay between A6 and B2 is TOS − TD and that between A2 and B6 is TOS + TD, where TOS is the time difference between INA and A6 (or INB and B6). The difference in the metastable time for LA1 and LB1 results in the doubling of the output delay between YP and YN. However, as shown in Fig. 2-9 (b), for input signals with a large time difference (TD–TOS), the delay between A6 and B2 is extremely small, resulting in a longer settling time for LA1. Consequently, the output time difference is over-amplified. As shown in Fig. 2-9 (b), the magnification ratio increases from 2 to 2.875.
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Figure 2-8 SR-latch-type TA schematic diagram.
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2.3.2 Dependent Discharge Time-Difference Amplifier [2]
In [2], a dependent discharge time-difference amplifier is proposed which uses a cross-coupled circuit structure to get a gain of two. A simplified schematic is shown in Figure 2-10. Initially, node A and B are precharged to VDD when IN+ and IN- are low.
OUT+ and OUT- are kept low and waiting for low to high transitions of IN+ and IN-.
When IN+ or IN- rising edge occur, node A or B start to be discharged and the discharging is performed by self-inverter path (M1 or M3) and a dependent path (M2 or M4). The strength of one dependent path is determined by the discharging status of the counterpart node (M2 gate is controlled by node B and M4 gate is controlled by node A).
The first transition makes the other transition slower by reducing the strength of the dependent path, resulting in an amplified time difference. Assume M1-M4 are identical, the first discharging is performed by two identical pull-down paths but the second discharging is performed by only one pull-down path. Therefore, the gain is roughly two when the IN+ and IN- rising edge are closed.
Figure 2-10 2X cross-coupled TA [2]
2.3.3 Pulse-Train Based Time-Difference Amplifier [26]
The principle of the pulse-train based TA is illustrated in Fig. 2-11[26]. The idea is to generate N copies of pulses with the same pulse-width of Tin. It can be equivalent to a wider pulse with a pulse-width N×Tin. Since the N input pulses of OR gate cannot be overlapping, the buffer delay time 𝜏𝑑 in the delay chain should be longer than pulse-width Tin. This results in limiting the TA speed. In addition, the balanced rise time and fall time of each buffer is necessary in order to maintain the same pulse-width on N inputs of OR gate. The input switches of OR gate determine the number of pulses that goes into the OR gate and thus controls the gain.
Figure 2-11 Pulse-train based TA [26]
2.3.4 Closed Loop Controlled Time-Difference Amplifier [27]
In [27], a time difference amplifier whose gain is controlled by a closed loop is proposed. The principle of the proposed TA is illustrated in Fig. 2-12. The delay time of each delay cell is variable and can be changed by a control pin. In Fig. 2-12 (b), the delay time is 4:1 when the control signal is H:L. The connection of two cross-coupled delay chains is shown in Fig. 2-12 (a). Every delay cell output is used to control the delay time in another cross-coupled delay chain. When the rising edge pass through a delay cell, then the output goes high and another cross-coupled cell’s delay time will become 4. For example, if the rising edge difference between in1 and in2 is 2 initially, they start to pass through the different delay chain respectively. In1 is from the left side to the right side and in2 is from the right side to the left side. Their rising edges will
meet in where the bold arrows point. Then the delay time of all delay cells are frozen.
The rising edge of in1 travel 5 delay cells and switch 5 delay cells to ―H‖ in the bottom
delay chain. The rising edge of in2 travel 3 delay cells and switch 3 delay cells to ―H‖ in the top delay chain. Eventually, the output rising edge difference between out1 and out2 is 8 which is amplified by 4.
Fig. 2-13 shows a block diagram of the proposed closed loop control TA. A
delay-locked loop (DLL) is employed to adjust the delay ratio of the variable delay cell with its delay switch of H/L to be 4. When the loop is locked, the delay ratio of the replica delay cell with its delay ratio H/L is adjusted to be 4, and the Vctrl is used to control the main delay cell of the cross-coupled delay chains.
Figure 2-12 Basic idea of the proposed TA in [27]. (a) Cross coupled chains. (b) Variable delay cell (c) Timing diagram.
Figure 2-13 TA using DLL-like closed-loop control. [27]