The test chip is designed for the SuperSpeed Universal Serial Bus (USB) 10 Gbps (USB3.1 Generation 2) specification. The proposed 1D-EOM circuit was included in the receiver side. This chip was designed and fabricated using a 64-nm CMOS process.
The layout area of the EOM is 60 µm × 450 µm and the total power consumption is 1.5 mW. Figure 4-19 shows the test chip die photograph and Figure 4-20 shows the power breakdown. The majority of power is consumed by two comparator circuits. STOD and DTOS blocks are also included. They all consume 70% of the total power. The major power consumers are high speed latch circuits. In addition, the VTC and logic circuit consumes 15% and 10% of the total power, respectively. The calibration circuit only consumes 5% because they are almost powered down after the calibration process is
finished. The 1D-EOM circuit was used to capture the receiver’s front-end equalizer output waveform and calculate its corresponding horizontal eye-opening. Then, the calculated result was compared to an expected eye-opening value. If too small, then the boost gain of the equalizer was enhanced to extend the horizontal eye-opening. The EOM results were updated every 64 µs.
Figure 4-19 Test chip die photograph.
Figure 4-20 Power consumption breakdown.
VTC 15%
Comparat or 70%
Calibration 5%
Logic 10%
The measurement setup is shown in Figure 4-21. In order to compare the real eye diagram and the proposed EOM, a test buffer circuit was built into the test chip to drive the off-chip equalizer output signal as well. Therefore, the real eye diagram was obtained using an oscilloscope. To verify this chip, a BER test system was used to generate a SuperSpeed USB 10 Gbps compliance test pattern, where the test channel was a 14-cm USB 3.1 Generation 2 cable plus a short printed circuit board trace. The receiver equalizer was adapted to an optimized gain setting. After that, the amount of random jitter in the BER test system input was adjusted and the EOM results were simultaneously monitored by logic analyzer.
Loopback BERT
Test buffer EOM data
FPGA
Power Supply
Logic Analyzer
Oscilloscope DUT
control
Figure 4-21 Measurement setup.
The measurement results are shown in Figure 4-22 (a) (b), Figure 4-23, and Figure 4-24 (a) (b) (c). The test condition is that the input has no random jitter. Figure 4-22(a) shows the test buffer eye diagram. The eye height is 140 mVpp and the eye width is 76 ps. Figure 4-22 (b) shows the six-bit 1D-EOM output and a finish indicator. The results are output by a logic analyzer. In this case, the 1D-HEOM six-bit output was 110101 (decimal value of 53), and the maximum value was 64. Figure 4-23 shows the HEOM results (decimal representation) against the input with different amounts of random jitter.
Figure 4-24(a) (b) (c) shows the eye diagram before and after receiver equalization. The EOM result is also demonstrated in the top-left corner of every eye diagram during equalizer adaptations. Table 4.2 provides a performance comparison of prior EOMs.
(a)
Reg_eom HEOM EOM_DONE
(b)
Figure 4-22 (a) Test buffer output eye diagram. (b) 1D-EOM output results.
Figure 4-23 HEOM results VS. Input with Different Random Jitter (RJ).
(a)
(b)
(c)
Figure 4-24 Eye diagram VS. HEOM results during equalizer adaptations. (a) Before equalization. (b) During equalization. (c) After equalization.
HEOM=6b’01 0100
HEOM=6b’11 0000
HEOM=6b’11
0101
Table 4.2 Performance comparisons of EOMs.
Reference Technology Type Power
(W) chapter. In order to precisely measure the eye-opening, the whole eye diagram must be reconstructed instead of choosing some eye masks to fit the eye diagram. However, this results in long computational times to calculate the probability density functions for all pixels and cannot easily be applied for real-time equalizer adaptations. With a trade-off between speed and accuracy, a one-dimensional EOM structure was proposed to monitor the horizontal eye-opening in the eye diagram. Since the proposed EOM does not employ a bit-by-bit data processing structure, sampling data with different phases in parallel is not necessary. Power consumption can be greatly reduced, and all complicated phase interpolation circuits can be replaced with the proposed phase
generator circuit. The mismatch problem that exists in the traditional phase interpolation circuits can be mitigated.
The EOM circuit was implemented and verified in a SuperSpeed USB 10 Gbps receiver prototype integrated chip using 64-nm CMOS technology. The measurement results demonstrated that the value reported by the horizontal EOM was closely correlated with the real eye width, which is helpful for equalizer adaptation. The total power consumption was 1.5 mW for a 1 V supply, which is much smaller than the traditional bit-by-bit data processing EOM.
Chapter 5 Conclusion
5.1 Summary
In this dissertation, several time-domain processing circuits as well as the design and analysis of these circuits are presented. In chapter 2, a brief overview of two critical time mode circuits, VTC and TA are introduced. Some state-of-the-art designs are also presented in this chapter. Next, in chapter 3, a high-speed time-based ADC (TADC) is proposed and demonstrated in 0.18-μm CMOS technology. In this chapter, a novel VTC circuit is proposed. A load tuning circuit in the proposed VTC provides an adequate control voltage to a symmetric-type delay cell for the improvement of linearity. The post-layout simulation result shows that the proposed VTC circuit can provide 7 to 8 bits of accuracy for the TDCs and the sampling frequency of the following TDCs can be up to 500 MHz. The measurement results of TADC are also presented at the end of this chapter.
Finally, a time-domain design example is proposed in chapter 5. In this
chapter, a multi-phase clock generator based on the VTC is proposed in the one-dimensional eye monitor (1D-EOM) circuit. It provides a sampling clock with an accurate phase difference for the EOM circuit. The proposed 1D-EOM circuit is implemented in 65-nm CMOS technology and the measurement results demonstrate that the value reported by the 1D-EOM can be used as a feedback parameter for equalizer adaptations. It occupies a small layout area and consumes less power than the conventional eye monitor circuit.