VTC design [35]

The proposed VTC consists of a load control circuit, VREF generator, dual path delay chains and a phase detector. The block diagram was depicted in Figure 3-3 (a).A load control circuit can be divided into a load tuning circuit and two delay replica-biasing circuits. The load tuning circuit converts the input signal VIN to a differential signals Vctrlp and Vctrln are the inputs of two delay replica bias. The delay replica bias circuit will control the output swing of the replica delay cell by a negative feedback and then generate two pairs bias voltages Vcsp(Vcsn) and Vbnp(Vbnn) for the real delay cells (DPx and DNx) biasing. Figure 3-3 (b) shows the corresponding waveforms of VTC.

Load Control

Figure 3-3 (a) Proposed VTC block diagram. (b) VTC output waveform.

The operation is described below. If Vctrlp is greater than Vctrln, the clock edge of CKP will lead CKN. In contrast, if Vctrln is greater than Vctrlnp, the result is inversed.

Since the transfer curve of the delay time versus the control voltage is nonlinear, a load

tuning circuit is needed for correcting this non-linearity. The delay replica bias circuit contains a replica of the delay cell, which controls the bias of the delay cell in order to force its output voltage to be clamped between 0 and Vctrlp,n. The dual path delay chain propagates the reference clock CK with a relevant delay time according to the delay control signals Vcsp,Vcsn,Vbnp and Vbnn. The delay chain output signals CKP and CKN have differential time difference properties and the waveforms shown in Figure 3-3 (b).

The purpose of the phase detector is to detect the VTC output signal in advance.

The lead (or lag) flag indicates the polarity of analog input. It facilitates preventing the VTC outputs from unnecessarily entering some comparator units of the subsequent flash TDC, thereby markedly reducing power consumption. Only two thirds of the comparator units are toggled during each code conversion. CKPd and CKNd are the delayed signals with respect to CKP and CKN for compensating the latency of the phase detector. The phase detector circuit was implemented using a D-Flip-Flop.

The proposed load tuning circuit is shown in Figure 3-4 (a).The NMOS input degenerated differential pair (MN3 and MN4) with a PMOS diode connected load (MP2~MP5) converts the input differential signals VP and VN into a differential delay control voltages Vctrlp and Vctrln. The PMOS diode connected load is used to match

the symmetric load of the delay cell in the dual path delay chain.

The delay cell with a symmetric load is proposed in [36]. It has a very broad delay range but the delay time is nonlinear with respect to the control voltage. In fact, the delay changes proportionally to 1/(VCTRL-VT), where VCTRL is control voltage of the symmetric delay cell and VT is the threshold voltage of the diode connected load (In our design is NMOS MNL1~MNL4 shown in Fig. 3-6 (a).). The transfer curve of delay time versus control voltage, VCTRL is shown in Figure 3-5 (a). Figure 3-5(a) also shows that the characteristic curve will shift due to different process corners. This offset will limit the input dynamic range and overload the following TDCs as well. In order to mitigate this effect, a VREF generator circuit has been added as shown in the Figure 3-4 (b). The purpose is to sense NMOS MN1 and PMOS MP1 threshold voltage and then amplify the summation of their threshold voltage (Vx) by (1+R2/R1). VREF serves as the supply voltage of the diode connected load (MP2~MP5) and the output source follower circuit (MP7 and MP8 are input transistors) which is shown in Figure 3-4 (b). At slow P and slow N corners, the PMOS and NMOS will have a higher threshold voltage. This implies that VX and VREF are also higher and will shift the delay control voltage Vctrlp and Vctrln to a higher level in order to compensate the lower speed of delay cell. Eq.

(3.3) is the design equation of VTC transfer gain. This compensation can be

demonstrated roughly using this equation. Figure 3-5 (a) and (b) show the illustrations of uncompensated and compensated VTC transfer curve. The output time variable is defined as the rising edge difference between the two delay chains output, CKP and CKN, and it can be derived as follows:

∵ ∆𝑇_𝑃,𝑁∝ 𝐶

≈ √ 1

respectively. VCTRLP and VCTRLN are the control voltage of P-side and N-side delay cells, N is the total number of delay cells in one delay chain, KP and KN are the current gain of PMOS diode connected load (MP2~MP5) in Figure 3-4 (b) and NMOS symmetrical load of delay cell (MNL1~MNL4) in Figure 3-6 (a). C is the output capacitance of all

delay cells and K is a constant. 𝑉_𝑇𝑁𝐿 is the threshold voltage of the NMOS symmetric load. |𝑉_𝑇𝑃 | and 𝑉_𝑇𝑁 are the threshold voltage of MP1 and MN1 in VREF generator

circuit in Figure 3-4 (a) and IB is their bias current. |𝑉_{𝑇 ,} |, |𝑉_{𝑇 ,} |, |𝑉_𝑇 |and |𝑉_𝑇 | are the threshold voltage of PMOS devices MP2,MP3,MP4,MP5,MP7 and MP8 in load

tuning circuit. To simplify this derivation, assume they are identical, and the threshold voltage is defined as|𝑉_𝑇|. By Eq. (3.1) and (3.2), the overall gain of VTC can be

expressed as G, and

G = ( ∆T

∆𝑉_𝐼𝑁)

=

Figure 3-4 (a) Load tuning circuit. (b) VREF generator.

Vctrl

The load tuning circuit is designed to provide a control voltage VCTRLP and VCTRLN

expressed as Eq.(3.1). From Eq. (3.2), the output time variable, ∆T is linearly proportional to the analog input voltage ∆VIN and the transfer gain G also derived in Eq.

(3.3). Moreover, a proposed VREF generator circuit for compensating the threshold voltage variation at different MOS corner and the result is marked with double horizontal lines in Eq. (3.3). The delay chain circuit is used to process the sampling clock CK and generate time difference signals that are to be measured and quantized by the following TDCs. The overall delay time Td at the kth sample can be represented as Eq. (3.4)

𝑇𝑑(𝑘) = 𝑁 × (𝑇𝑖𝑛𝑡 + 𝑉𝑖𝑛(𝑘) × 𝐺), Td < Ts at any sample k (3.4) Fs = 1 T⁄ _s < 1 (N × (𝑇𝑖𝑛𝑡 + 𝑉𝑖𝑛, 𝑚𝑎𝑥 × 𝐺))⁄ ， (3.5) 𝐺 < (T_s− N × 𝑇𝑖𝑛𝑡) (N × 𝑉𝑖𝑛, 𝑚𝑎𝑥)⁄ ， (3.6) T_res = 𝑇𝑑, 𝑚𝑎𝑥

2ⁿ = 𝑉𝑖𝑛, 𝑚𝑎𝑥 × 𝐺

2ⁿ < T_s− N × 𝑇𝑖𝑛𝑡

N × 2ⁿ ， (3.7)

Where Tint is the intrinsic delay of the symmetric delay cell, G is the VTC transfer gain, Tres is the time resolution of the time delay Td,max which is quantized into n bits, and N is the total delay cell number in the delay chain. In fact, Td should be less than a

TDC sample time Ts, implying the maximum allowed transfer gain and time resolution in following n-bit TDC will be as given in Eq. (3.6) and Eq. (3.7). For example, if the TDC sampling frequency is 500 MHz, the intrinsic delay time of a delay cell is 200 picoseconds, delay chain number is 4, and input is quantized into 6 bits, then the maximum allowed time resolution of the following TDC is 4.7 picoseconds. Eq. (3.5) also gives the maximum allowed sampling frequency of the following TDC if VTC gain, intrinsic delay and input range are known.

The delay chain circuit consists of a clock buffer, a number of delay cells, and a voltage slicer circuit. A source coupled pair with a symmetric load delay cell is adopted, as shown in Figure 3-6 (a). The left side of Figure 3-6 (b) is a closed loop delay replica biasing circuit. The negative feedback mechanism forces Vb to be approximately equal to Vctrl. Since the bias circuit is a half replica of the delay cell, the mechanism also forces the output voltage of the delay cell to be clamped to Vctrl. In order to operate at high speed, a modified open loop replica bias circuit is used to force Vb close to Vctrl, as shown in the right side of Figure 3-6 (c). Substituting the NMOS transistor MNB1 for the PMOS transistor MPS1 in the Figure 3-6 (b) and the gate voltage of MN1 is equal to Vctrl plus a NMOS threshold voltage.

The purpose of the voltage slicer circuit is to amplify the delay cell output to the

supply rail. It also contributes some nonlinearity in the VTC since the response time is not identical when a small or large swing input occurs at the slicer circuit. Fortunately, the delay chain with a large-scale output swing has a smaller delay time, which alleviates the design effort of the slicer since one can use a general amplifier circuit. The delay time of the slicer is also proportional to the delay time of the delay chain. Figure 3-7 shows the proposed slicer circuit. An operational transconductance amplifier with a dynamic tail current that is inversely proportional to Vctrl is used to further improve the linearity and power efficiency. The layout of the VTC circuit is completed using a 0.18µm CMOS process as shown in Figure 3-8.

Vbn Figure 3-6 (a) Symmetric delay cell circuit (b) Replica biasing circuit of the delay cell.

(c) A modified replica biasing circuit of the delay cell.

Vcs

Vcs1 VDD

Vip Vin Vout

Figure 3-7 A voltage slicer circuit.

Figure 3-8 VTC layout in whole chip. (Area is 400µm by 100µm).

The delay time mismatch in a dual-delay-line structure is more severe than that in a

single delay line. This mismatch further impairs the linearity of the VTC transfer gain.

In Eq. (3.9), the first two terms error are the threshold and current gain mismatch of PMOS MP2~MP5 in the load tuning circuit. The last two terms error are from the delay cells mismatch. Figure 3-9 shows a Monte-Carlo simulation result at zero analog input of VTC. There are a total of 300 runs. The simulation result shows that the peak-to-peak delay variation is less than 25 picosecond. This is the minimum distinguishable resolution without calibration.

This variation of output time variable of VTC can be calibrated to further improve its resolution if necessary. For instance, the bias voltage of the delay cells can be fine-

tune by using a replica delay cell while the delay time is locked by a delay-locked loop to reduce the mismatch effect. A cyclic delay structure can also reduce the number of delay element to just one, but a cyclic delay structure is difficult to operate at high speed.

Figure 3-9 Monte-Carlo simulation results of VTC at zero analog input.