Chapter 2 Techniques
2.3 Electrical analysis techniques
The nano-probe system is a transistor level electrical measurement tool. The nano-probe system in this work is DCG sProber, which equipped four positioners with 2 nm resolution of movement [57]. The sProber can be installed into the existing SEM and FIB for cost saving.
As the transistor dimension going into nano-scale dimension, the major challenges of nano-probe system are the how small of tip size can be made and how many tip counts can be put in a small area. Figure 2-7(a) shows the DCG nProber which with 8 nano positioners [58].
Figure 2-7(b) is a SEM image from nProber, showing the 8 nano tips probe in the metal 1 layer of SRAM [58]. The tip radius is smaller than 50 nm [57]. The DCG’s system also has anti-contamination function for offering a low resistance measurement [57].
The major application of a nano-probe system is to measure the electrical characteristic of a transistor. Because the transistors are covered by metal layers and passivation layer, the sample was polished to contact layer for electrical measurement. In this work, the nano tips probe on the contact to measure the Id-Vg curve of the LDMOS. In addition, nano-probe was used to bias the n-well and p-well in a reverse bias condition, enhancing the SEPC effect in SEM. The missing dopant contrast is restored after the bias is triggered on the diode nodes, offering a new application of nano-probe system.
With the feasibility of operation, several new applications have been developed. Stallcup
proposed bitcell pulsing measurement method to isolate the defective transistor of the SRAM [58]. Other applications include using electron beam induced current (EBIC) to characterize the carrier life time and electron beam absorption current to isolate the continuity failure of backend metal layers [57]. However, the electron beam irradiation may cause transistor degradation and the primary electron beam energy should be as low as possible.
2.3.2 Conductive atomic force microscope (C-AFM)
AFM uses a tiny tip to scan the specimen surface and record the atomic force interaction between tip and specimen [59, 60], including electrostatic force, van der waals force, and magnetic force…[59, 60]. Since the AFM has the atomic scale resolution, the AFM is widely adopted to measure the electrical properties, magnetic properties, and topology information of the specimen. The operation modes of AFM have non-contact mode, contact mode, and tapping mode. Figure 2-8 shows the schematic to illustrate the operation principle of a C-AFM [61].
The model of AFM in this work is Veeco Innova. The Innova is a contact mode AFM
which using a metal tip to measure the conductivity of specimen. The measuring current ranges from 2 pA to 1 µA. In this work, C-AFM was used to isolate the leakage p+/n-well
junction. The current map of C-AFM result indicates the leakage p+/n-well junction appeared in every alternative row. The misalignment of the p-well mask layer is identified as the root cause of leakage.
With high sensitivity in electrical measurement, C-AFM can be used to isolate high resistance issues and small leakage issues in CMOS technology. A four tips C-AFM system was also developed to measure the transistor’s electrical characteristic. The benefit of transistor measurement by C-AFM is no damage of transistor due to the electron beam irradiation. However, without the assistance of SEM, the transistors’ location is located by the scanning of tips. For soft material like copper, the scratch induced by the tip may initiate unwanted short path between metals, limiting the application in the metal layer probing.
Figure 2-1 (a) The polish mechine Allied MultiprepTM. (b) Diamond films with colors to indicate different abracive effect. (c) The polsih head for cross-section sample preparation. [52]
Figure 2-2 Schematic drawing indicates characteristic signal generated by interaction of primary electron beam and specimen. [17]
Figure 2-3 Schematic drawing shows the distribution of emitted electrons after the bombardment of primary electron beam. [24]
Figure 2-4 Schematic drawing shows the escape depth of silicon diode with FIB sample preparation. [48]
Figure 2-5 Secondary electron yield (δ) versus primary electron energy EPE. [24]
Table 2-1 The maximum secondary electron yield (δm) and maximum primary electron energy (EPE
m) for CMOS materials. [24].
Figure 2-6 A cross-section FIB image after the precise milling by FIB. [56]
Figure 2-7 (a) DCG nProber with 8 nano positioners. (b) SEM image showing 8 nano tips probe in the metal 1 layer of SRAM bitcell. [58]
Figure 2-8 Schematic drawing shows the operation principle of C-AFM.
[61].
Chapter 3
SEPC in contacts by SEM primary electron energy adjustment
3.1 Introduction
With the assistance of electronic design automation (EDA) software and the demanding of chip functionality, the number of transistors in a VLSI chip can exceed billions. However, a tiny defect in a transistor can cause malfunction of the entire chip. An efficient fault isolation method is important to maintaining product with high yields and performance. The SEPC method is widely used to isolate connectivity failures and gate oxide ruptures in VLSI chips [22, 23]. The SEPC effect is correlated to the surface potential of the area of interest [20, 21].
For CMOS technology, four contact nodes are used—the n+/p-well node, p+/n-well node, poly gate node, and well node [15, 43]. The conventional SEPC method uses a low EPE=1 keV [62, 14]. However, a low EPE cannot distinguish between these four node types. For instance, the contrast between p+/n-well nodes and well nodes is with the same brightness under the low EPE condition, indicating that traditional SEPC cannot detect p+/n-well junction leakage to wells. In this work, primary voltage adjustment is applied to overcome this limitation.
3.2 Experimental details
In this experiment, the sample is a functional SRAM manufactured using 0.15 µm technology. A p-type (100) Si wafer with 8–12 Ohm-cm resistivity was the substrate. The
sample was processed with the standard CMOS process up to the Metal 3 layer.
All SEM images were obtained with a Hitachi S4700 equipped with an (E×B) filter.
Figure 3-1 illustrates the E×B filter function. The typical SE energy was <50 eV [24]. The E×B filter removes the high-energy tail of the BSE and guides the SE to the upper detector to
enhance the SEPC effect on Si. The SEM operating conditions were optimized for diode visualization. The SEPC image was obtained using an EPE of 1 keV and 5 keV. The SRAM chip with normal function was fabricated and manually polished contac for SEPC inspection.
Notably, a FIB from FEI DB235 was used for cross-sectional inspection.
3.3 Results and discussion
3.3.1 SEPC result by primary electron energy adjustment
Two functional SRAM samples were polished to contact layer and the SEM image was acquired with 1 keV and 5 keV EPE, respectively. Figure 3-2 shows the SEM image with 1 keV EPE. In this image, the contrast of the contact can be classified into three levels. The contrast of the polysilicon contact, n+/p-well contact, and p+/n-well contact shows the low contrast, moderate contrast and high contrast, respectively. Figure 3-3 shows the SEM image obtained with 5 keV EPE. Contrast in the image also has three levels, but differs trend from that of Fig 3-2. The contrast of the polysilicon contact, n+/p-well contact, and p+/n-well contact shows the high contrast, low contrast and moderate contrast, respectively. Contrast with different EPE values behaves differently.
The SEPC arises from different surface potentials after primary electron (PE) irradiation.
The source of surface potential is the yield of the SE, which is not equal to that of the primary electrons. SE yield (δ) is the dividing of SE number by PE number. Figure 3-4 shows the tungsten SE yield (δ) as a function of EPE [24]. The surface potential will be positive charging when the SE yield is larger than 1, and negative charging when the SE yield is < 1. Based on Seiler’s study, the tungsten surface will be positive charging at EPE=1 keV and negative charging at EPE=5 keV [24].
Figure 3-5(a) is a schematic showing the contrast behavior when EPE is 1 keV. According to the traditional SEPC effect, when a sample was exposed to the 1 keV electron beam, a positive charge was generated on the sample surface. On a floating contact, such as a polysilicon contact, the positive charge remained on the surface, and reduced the number of SEs collected by the detector. Thus, the polysilicon contact has low contrast in the SEM image. For a positive charge, the p+/n-well is forward biased, such that the positive charge can be discharged through the p+/n-well to the substrate. Therefore, the p+/n-well contact will be in a higher contrast. Conversely, the n+/p-well is reverse biased for the positive charge. Thus, positive charges are seldom discharged through the n+/p-well to the substrate and remain on the surface of the contact connected to the n+/p-well, such that the contact on n+/p-well will be lower contrast. For the grounded contact, the positive charge will be discharged to the substrate, and will not reduce the number of SEs collected by the detector. Thus, the grounded
contact is brighter than the floating contact in the SEM image.
Figure 3-5(b) shows a schematic explaining contrast behavior when EPE is 5 keV. A negative charge will result on the sample surface (Fig. 3-3). Under this negative charging condition, the negative charge will be maintained on the polysilicon contact surface and the number of SEs collected by the detector will increase; the polysilicon contact is bright in the SEM image. For negative charging, the p+/n-well is reverse biased, and the negative charge cannot be discharged easily through the p+/n-well; thus, the p+/n-well contact will have high contrast. The n+/p-well contact is forward biased for the negative charge, such that the negative charge can be discharged through n+/p-well to the substrate. The n+/p-well contact will be low contrast in SEM image. For a grounded contact, the negative charge will be discharged to the ground and will not increase the number of SEs collected by the detector;
thus, the grounded contact is darker than the floating contact in the SEM image.
Table 3-1 summarizes the contrast behavior of contacts under the 1 keV and 5 keV EPE conditions. According to table 3-1, identifying the defective contact is easy when SEM images were acquired under both 1 keV and 5 keV.
3.3.2 Application of primary electron energy adjustment in defect isolation
The sample is a 0.15-µm SRAM chip that suffers a single bit failure. The sample is planar polished to Metal 1 layer for SEPC inspection to find any abnormality in the Metal 1
layer. Figure 3-6 shows the SEM image under 1 keV EPE. However, no abnormality was identified in the SEM micrograph. Thus, EPE was increased to 5 keV and another SEM micrograph was acquired, as shown in Fig. 3-7. One C-shaped Metal 1, which acts as the storage node of SRAM, is significantly brighter than the other C-shaped Metal 1. Thus, a cross-sectional inspection is performed by FIB, which reveals a porous n+/p-well contact in the failing cell, as shown in Fig. 3-8.
The abnormal SEPC from this sample cannot be identified at EPE=1 keV because three contacts are under Metal 1 layer: one connected to the p+/n-well another connected to the n+/p-well, and the last connected to polysilicon. When the sample is exposed to a 1 keV EPE condition, positive charges were generated on the sample surface. According to the principle of SEPC described previously, positive charges can be discharged by the contact connected to the p+/n-well. Thus, each Metal 1 can discharge its positive charges via its normal contact to the p+/n-well and all Metal 1 SEPC would be normally bright. In this case, the defect was an open contact connected to the n+/p-well. Therefore, one cannot detect this defect by EPE=1 keV. Conversely, negative charges will be generated on the sample surface when the sample is exposed to EPE=5 keV. Negative charges will be discharged by the normal n+/p-well contact for all normal cells except the open contact. Thus, the negative charges were not discharged on abnormal cells, and would increase the number of SEs collected by the detector; thus, abnormal C-shaped Metal 1 was brighter than other metals. With the EPE=5 keVcondition,
this defect may be identified because high resistance located on n+/p-well contact cannot be identified when EPE=1 keV.
3.4 Summary
In summary, the SEPC exhibits different contrast effects by adjusting the primary electron energy. The proposed SEPC procedure can distinguish between all contact types in an SRAM chip, overcoming the weakness of traditional SEPC. The SEPC images under varying primary electron energies were acquired experimentally and discussed. The surface-charging model explained the contrast behavior well. Finally, the proposed SEPC procedure was applied to isolate a porous n+/p-well contact, which cannot be found via the tradition SEPC method.
Figure 3-1 Sketch illustrates the function of E×B filter. Secondary electron (SE) is with low energy and could be guided to the upper detector by E×B filter..
Figure 3-2 The SEPC image of contacts from a 0.15 µm SRAM with 1 keV EPE.
Figure 3-3 The SEPC image of contacts from a 0.15 µm SRAM with 5 keV EPE.
Figure 3-4 The schematic curve shows secondary electron yield (δ) as a function of EPE for tungsten.[9]
Figure 3-5 (a)Schematic illustrates the SEPC effect under 1 keV EPE. (b)Schematic illustrates the SEPC effect under 5 keV EPE.
Figure 3-6 The SEPC image of metal 1 from a 0.15 µm SRAM with 1 keV EPE.
Figure 3-7 The SEPC image of metal 1 from a 0.15 µm SRAM with 5 keV EPE.
Figure 3-8 The cross-section image shows porous contact in n+/p-well node by FIB sample preparation.
Table 3-1 Summary of the contrast behavior of contacts under the 1 keV and 5 keV EPE conditions.
Chapter 4
Junction profiling and junction leakage isolation by SEPC
4.1 Introduction
Developments in microelectronic integrated circuit technology shrink transistor dimensions to increase device performance. The scaling down of semiconductor devices was initially achieved by simply reducing the physical width of the wells. The first issue related to downscaling the physical well width is controlling photomask alignment and dimension uniformity [44, 45]. Poor control can create unwanted leakage paths. Numerous reports have described how to inspect the distribution of implanted dopant profiles in junctions, for instance, chemical delineation uses nitric and fluride acids to selectively etch the heavily doped areas [63]. However, this method has difficulty revealing the precise well profile due to low dosage of the dopants. In addition, wet etching methods are destructive, meaning that the doping area will be etched out permanently. Other methods such as secondary ion mass spectrometry and scanning capacitance microscoprope could work for dopant profile inspection, but they provide insufficient spatial resolution for small areas [64, 65].
In the chapter 3, author introduces a new SEPC procedure to isolate the defects happen in contact and metal layers. Recently, secondary electron potential contrast (SEPC) using
scanning electron microscope (SEM) also demonstrated a strong applicability to dopant profile imaging [26, 27]. The SEPC signals arise from differences in the built-in potential between different doping areas. Since this inspection method uses the built-in potential of a diode, it affords a non-destructive approach to doping inspection. Numerous publications have conducted studies on materials with wide energy bandgaps, such as SiC [32]; however, SEPC signal inspection is more difficult with silicon having a small band gap energy of 1.1 eV. The damaged layer generated by sample preparation method is also an important factor for dopant inspection. In this chapter, we study three methods of sample preparation and provide optimum condition for dopant inspection. Second we illustrate SEPC inspection of silicon p+/n-well junctions and also develops a dynamic trigger for isolating p+/n-well junction leakage.
4.2 Experimental details
A SE is generated by the inelastic collision between the primary electron beam and substrate. The energy of the SE is <50 eV and escape depth is <40 nm [48]. Kazmianm et al.
demonstrated that the sample preparation procedure is a critical factor for dopant contrast [48].
Thus, before conducting the SEPC experiment, three different sample preparation methods are investigated. The experiment uses a Hitachi SEM S4700. With its good through-the-lens SE detector, the SE image contrast of different dopants is both sharp and clear. This study also utilized a standard SEM operating condition to view SEPC images using different methods.
That is, accelerating voltage is 1 keV and emission current is 15 uA. In this study, 0.22 µm and 0.15 µm logic chips were used as examples. Three methods were applied to prepare samples for dopant contrast inspection on doped silicon regions. These methods are manual polishing, Ar-sputtering, and wet solution etching. Significant contrast is clear on freshly cleaved doped silicon, and contrast is enhanced after a NH4F chemical treatment [53]. This removes the oxide layer and passivates the surface by saturating dangling bonds with hydrogen [53]. The primary goal is to change the state of the silicon surface. Ammonium fluoride solution (5 grams of NH4F crystals in 30ml water) was selected because it produces an atomically flat surface compared with aqueous HF acid, which is more commonly used [66]. In this study, bare silicon samples were dipped in NH4F solution and inspected by SEM.
After the identification of the optimum sample preparation method, we adopted these experiences in a real case, in which a SRAM suffers high standby current failure. The specimen in this study was a static random access memory (SRAM) that was manufactured using 0.11 µm IC technology. A p-type (100) silicon wafer with a resistivity of 8–12 Ohm-cm served as the substrate. After shallow trench isolation (STI), phosphorous dopants were implanted with a dosage of 2.6 × 1013 ions-cm−2 and an ion energy of 150 keV into the silicon wafer to form the p-well, while boron implantation was carried out to form a p-well region with a dosage of 3.0 × 1013 ions-cm−2 and an ion energy of 160 keV. After the well formation process, p+-type source and drain regions were formed by boron implantation with a dosage of
1.5 × 1015 ions-cm−2 and ion energy of 5 keV. Thermal activation at 1000°C for 5 s and metallization were carried out sequentially as formal procedures. The sample was plane polished to the contact layer for conductive atomic force microscope (C-AFM) measurements.
The sample was manually polished to the cross section site of interest for cross sectional SEPC inspection. A Hitachi S4700, equipped with a through-the-lens E×B detector, was the major tool for SEPC inspection. An optimum SEM operation conditions were set to view the image of the diode. The secondary electron comes from an inelastic collision between the primary electron and the inner shell electron. The energy of the secondary electron is typically smaller than 50 eV. It is well known that the built-in potential of a diode can be expressed as a function of dopant concentrations:
)
where k is the Boltzmann constant, T is the absolute temperature, q is the elementary charge, and Na and Nd are the concentration of the acceptors and donors, respectively. Ni is the intrinsic carrier concentration of silicon. For silicon, the maximum built-in potential is equal to its band gap energy of 1.1 eV.
4.3 Results and discussion
4.3.1 Comparison of sample preparation methods for SEPC inspection
Manual polishing removes the layer above the silicon. An NH4F dip is then the most
convenient and easy method for removing the rest of the layer on the silicon surface. However, identifying a precise position in a chip is difficult. Without careful inspection, over-polishing or under-polishing may lead to failed sample preparation. Further, the repeatability of manual polishing is poor. Figure 4-1 shows the manual polishing result.
After removing the layers above the doped silicon, Ar sputtering was used to change the state of the silicon surface. The Ar-sputtering uses a Gatan Model 693 to bombard the silicon surface, slightly damaging the implant region. This method produces the poorest SEPC results.
Figure 4-2 only shows the n/p well contrast; implant details are not observed.
The final method uses HF acid to remove all layers above the silicon before dipping the
The final method uses HF acid to remove all layers above the silicon before dipping the