Chapter 1 Introduction
1.8 Organization of the thesis
In chapter 1, the CMOS technology revolutions and process characterization challenges are introduced. We also have brief overview of the physical and electrical properties of the pn diode. The applications of CMOS technology in the logic circuit, SRAM, and LDMOS are also addressed in chapter 1. Additionally, the overview of defect isolation and dopant profiling using SEPC, and techniques for dopant profiling are also summarized in chapter 1. In chapter 2, the experimental instruments, sample preparation methods, electrical and physical characterization techniques are presented. This chapter introduces the secondary electron in SEM, sample milling tool FIB, electrical measurement tool nano-probe system and AFM.
In chapter 3, the SEPC effect with varying primary electron beam energy is investigated.
A procedure is suggested to distinguish all node types in chip. Finally, this new procedure is applied in a real case and isolates defect successfully. Next, in chapter 4, the sample preparation methods for SEPC in dopant contrast inspection are examined. And a application of SEPC in p+/n-well junction leakage is presented. In chapter 5, this chapter investigates the use of SEPC with an in-situ nano-probe biasing to examine a silicon p+/n-well junction. The SEPC image is digitalized to elucidate the physics of diode. In Chapter 6, the mismatch mechanism in a current mirror was investigated using a SEM with in-situ nano-probe biasing.
In Chapter 7, we summarize the experimental results and give a conclusions and suggestions in future works.
Figure 1-1 Transistor counts of microprocessor (thousands) versus years. [1]
Figure 1-2 Logic technology node and transistor gate length over time. [2]
Figure 1-3 (a) Band gap diagram of p-type and n-type semiconductors. (b) Band gap diagram of a p/n junction in thermal equilibrium. [7]
Figure 1-4 (a) The space charge distribution of a linearly-graded junction.
(b) The electrical field of the junction. (c) The electrical potential of the junction. (d) The band diagram of the junction [7]
Figure 1-5 (a) The band diagram of a diode under thermal equilibrium. (b) The band diagram of a diode in forward bias condition. (c) The band diagram of a diode in reverse bias condition. [7]
Figure 1-6 The current voltage characteristics of the diode. [7].
Figure 1-7 (a) The radiation mechanism of a forward biasing diode. (b) The photon detection mechanism of reverse biasing diode. [8]
Figure 1-8 Schematic illustrats the cross-sectional structure of the CMOS technology.
Figure 1-9 (a) The circuit of a SRAM bit cell. (b) The layout pattern of a SRAM bit cell.
Figure 1-10 The cross-sectional structure of the lateral double diffused negative metal oxide semiconductors (LDNMOSs). [13]
Figure 1-11 The simulation result of electrical field above the unbiased SiC junction surface due to the built-in potential [32]
Figure 1-12 (a) SEPC image on a Si test structure. (b) SEM contrast profile.
(c) SIMS depth profile. [27]
Figure 1-13 The difference of SE intensity between p region and n region as a function of bias voltage. [27]
Figure 1-14 Schematic illustrates the SCM operation principle. [36]
Figure 1-15 Schematic illustrates the KFPM operation principle. [37]
Figure 1-16 The SEPC images prepared by different methods (a) The cleaving result. (b) The polishing result. (c) The FIB milling result. (d) SEPC intensity curve across junction. [48]
Chapter 2 Techniques
2.1 Sample preparation process 2.1.1 Planar sample preparation
The purpose of sample preparation is to make the specimen ready for physical and electrical characterization through mechanical and chemical treatment. In this work, the specimen is an IC chip with one poly layer and five metal layers. Planar sample preparation is using mechanical polish method to approach the target layer. The specimen is polished to contact layer for electrical measurement by nano-probe system or AFM. The mechanical polishing tool used in this work is Allied MultiprepTM and its picture is shown inFigure 2-1(a) [52]. Figure 2-1(b) shows diamond films with different color to indicate different abrasive effect [52]. The diamond film is changed from coarse to fine for minimizing the scratch in specimen surface.
2.1.2 Cross section sample preparation
The Allied MultiprepTM is also can be used in cross-section sample preparation after changing the polish head. Figure 2-1(c) shows the polish head for corss-section sample preparation [52]. In this work, the specimen is prepared in cross-section for dopant profile inspection.
2.1.3 Chemical delayer and Ar sputtering
The disadvantage of mechanical polish method is that it generates a damaged layer on the specimen surface, hindering the SEPC inspection. Chee et al reported that the chemical solution containing 40% NH4F can remove the oxide layer in Si surface and passivate the silicon surface [53]. Our study also confirms the BENEFIT effect of NH4F treatment in SEPC inspection [54]. For active area inspection, using HF solution is the most effective way for dielectric layer removing. In this work, the HF solution is used to remove the oxide layer above the active layer. In addition to chemical treatment, the Ar sputtering is also used to minimize the damaged layer thickness resulting from mechanical polishing. The apparatus we used in this work is Gatan Model 693.
2.2 Material analysis
2.2.1 Scanning electron microscope (SEM)
SEM was a primary electron beam to scan the specimen surface and collects the ejected electron by detector. The SEM model in this work is Hitachi S4700, which using field emission gun in primary electron beam generation. The interactions of primary electron beam with specimen generates characteristic signals like secondary electrons (SE), backscattered electrons (BSE), Auger electrons, and X-ray, and as shown in Figure 2-2 [17]. Figure 2-3 shows the distribution of emitted electrons after the bombardment of primary electron beam.
[24]. The secondary electron is the inelastic collision result between primary electron with
specimen and it is energy is smaller than 50 eV. On the contrary, backscattered electron is result from the elastic collision and its energy is close to the primary electron energy. Since the secondary electron energy is small, its escape depth is close to the surface, about 37 nm [48]. Figure 2-4 shows the escape depth of Si diode with FIB sample preparation [48]. The spatial resolution of the SEM is determined by the probe size of SEM. The specification of S4800, the upgrade model of S4700, possesses a 2 nm spatial resolution at 1 keV [56].
Since the energy of SE is less than 50 eV and majorly distributes at 4 eV, making SEM contrast with high correlation to the specimen surface potential [24]. SEPC shows lower contrast with positive potential. The traditional SEPC uses the fixed primary electron energy at 1 keV to isolate the continuity failure in IC [23]. The source of specimen surface potential
comes from surface charging after electron irradiation [24]. Figure 2-5 shows the schematic to illustrate the surface charging effect [24]. The SE yield (δ) is the division of emission electron number by injection electron number.δ > 1 results in positive charging in the surface and negative charging when δ < 1. Table 2-1 shows the δ and maximum primary electron energy
EPEm for CMOS materials [24]. The traditional SEPC condition 1 keV will result a positive charging in the specimen. In this work, we uses EPE =5 keV to make a negative charging in the specimen. The sample was polished to contact layer and irradiate by 1 keV and 5 keV electron beam, respectively. The SEPC images of contacts were recorded and a discussion is made to explain to contrast behavior. The second part of the thesis investigates SEPC with in-situ
nano-probe biasing to examine 2D dopant profile inspection. The dopant contrast is enhanced by nano-probe biasing and a series image process work is made to elucidate the physics of device.
The spatial resolution for SEPC is limited by the probe size of the inspection tool. Castell et al have suggested a 0.1 nm probe size of SEM for dopant mapping on the nanotechnology
age [6]. In this work, the spatial resolution of S-4700 is about 2 nm. Recently Helium Ion Microscopy (HeIM) is a new tool with probe size that is as small as 0.25 nm. Jepson et al have reported SEPC mechanism in HeIM is similar to SEM [46, 47]. Their further inspections observed that the SEPC spatial resolution is improved in HeIM, making HeIM an ideal candidate for nano-scale dopant mapping in the future [46, 47].
2.2.2 Focused ion beam (FIB)
The operation of FIB is similar to SEM, which uses a focus ion beam to image the specimen instead of focused electron beam used in SEM. The interaction between ion beam and specimen also generates secondary electron and could be used to form an image.
Additionally, the mass and momentum of ion is far more than electron, FIB will sputter the specimen surface and be a precision milling tool. The FIB apparatus used in this work is FEI DB235. Figure 2-6 shows the precise cross-sectioned milling capability of a FIB [56].
2.3 Electrical analysis 2.3.1 Nano-probe system
The nano-probe system is a transistor level electrical measurement tool. The nano-probe system in this work is DCG sProber, which equipped four positioners with 2 nm resolution of movement [57]. The sProber can be installed into the existing SEM and FIB for cost saving.
As the transistor dimension going into nano-scale dimension, the major challenges of nano-probe system are the how small of tip size can be made and how many tip counts can be put in a small area. Figure 2-7(a) shows the DCG nProber which with 8 nano positioners [58].
Figure 2-7(b) is a SEM image from nProber, showing the 8 nano tips probe in the metal 1 layer of SRAM [58]. The tip radius is smaller than 50 nm [57]. The DCG’s system also has anti-contamination function for offering a low resistance measurement [57].
The major application of a nano-probe system is to measure the electrical characteristic of a transistor. Because the transistors are covered by metal layers and passivation layer, the sample was polished to contact layer for electrical measurement. In this work, the nano tips probe on the contact to measure the Id-Vg curve of the LDMOS. In addition, nano-probe was used to bias the n-well and p-well in a reverse bias condition, enhancing the SEPC effect in SEM. The missing dopant contrast is restored after the bias is triggered on the diode nodes, offering a new application of nano-probe system.
With the feasibility of operation, several new applications have been developed. Stallcup
proposed bitcell pulsing measurement method to isolate the defective transistor of the SRAM [58]. Other applications include using electron beam induced current (EBIC) to characterize the carrier life time and electron beam absorption current to isolate the continuity failure of backend metal layers [57]. However, the electron beam irradiation may cause transistor degradation and the primary electron beam energy should be as low as possible.
2.3.2 Conductive atomic force microscope (C-AFM)
AFM uses a tiny tip to scan the specimen surface and record the atomic force interaction between tip and specimen [59, 60], including electrostatic force, van der waals force, and magnetic force…[59, 60]. Since the AFM has the atomic scale resolution, the AFM is widely adopted to measure the electrical properties, magnetic properties, and topology information of the specimen. The operation modes of AFM have non-contact mode, contact mode, and tapping mode. Figure 2-8 shows the schematic to illustrate the operation principle of a C-AFM [61].
The model of AFM in this work is Veeco Innova. The Innova is a contact mode AFM
which using a metal tip to measure the conductivity of specimen. The measuring current ranges from 2 pA to 1 µA. In this work, C-AFM was used to isolate the leakage p+/n-well
junction. The current map of C-AFM result indicates the leakage p+/n-well junction appeared in every alternative row. The misalignment of the p-well mask layer is identified as the root cause of leakage.
With high sensitivity in electrical measurement, C-AFM can be used to isolate high resistance issues and small leakage issues in CMOS technology. A four tips C-AFM system was also developed to measure the transistor’s electrical characteristic. The benefit of transistor measurement by C-AFM is no damage of transistor due to the electron beam irradiation. However, without the assistance of SEM, the transistors’ location is located by the scanning of tips. For soft material like copper, the scratch induced by the tip may initiate unwanted short path between metals, limiting the application in the metal layer probing.
Figure 2-1 (a) The polish mechine Allied MultiprepTM. (b) Diamond films with colors to indicate different abracive effect. (c) The polsih head for cross-section sample preparation. [52]
Figure 2-2 Schematic drawing indicates characteristic signal generated by interaction of primary electron beam and specimen. [17]
Figure 2-3 Schematic drawing shows the distribution of emitted electrons after the bombardment of primary electron beam. [24]
Figure 2-4 Schematic drawing shows the escape depth of silicon diode with FIB sample preparation. [48]
Figure 2-5 Secondary electron yield (δ) versus primary electron energy EPE. [24]
Table 2-1 The maximum secondary electron yield (δm) and maximum primary electron energy (EPE
m) for CMOS materials. [24].
Figure 2-6 A cross-section FIB image after the precise milling by FIB. [56]
Figure 2-7 (a) DCG nProber with 8 nano positioners. (b) SEM image showing 8 nano tips probe in the metal 1 layer of SRAM bitcell. [58]
Figure 2-8 Schematic drawing shows the operation principle of C-AFM.
[61].
Chapter 3
SEPC in contacts by SEM primary electron energy adjustment
3.1 Introduction
With the assistance of electronic design automation (EDA) software and the demanding of chip functionality, the number of transistors in a VLSI chip can exceed billions. However, a tiny defect in a transistor can cause malfunction of the entire chip. An efficient fault isolation method is important to maintaining product with high yields and performance. The SEPC method is widely used to isolate connectivity failures and gate oxide ruptures in VLSI chips [22, 23]. The SEPC effect is correlated to the surface potential of the area of interest [20, 21].
For CMOS technology, four contact nodes are used—the n+/p-well node, p+/n-well node, poly gate node, and well node [15, 43]. The conventional SEPC method uses a low EPE=1 keV [62, 14]. However, a low EPE cannot distinguish between these four node types. For instance, the contrast between p+/n-well nodes and well nodes is with the same brightness under the low EPE condition, indicating that traditional SEPC cannot detect p+/n-well junction leakage to wells. In this work, primary voltage adjustment is applied to overcome this limitation.
3.2 Experimental details
In this experiment, the sample is a functional SRAM manufactured using 0.15 µm technology. A p-type (100) Si wafer with 8–12 Ohm-cm resistivity was the substrate. The
sample was processed with the standard CMOS process up to the Metal 3 layer.
All SEM images were obtained with a Hitachi S4700 equipped with an (E×B) filter.
Figure 3-1 illustrates the E×B filter function. The typical SE energy was <50 eV [24]. The E×B filter removes the high-energy tail of the BSE and guides the SE to the upper detector to
enhance the SEPC effect on Si. The SEM operating conditions were optimized for diode visualization. The SEPC image was obtained using an EPE of 1 keV and 5 keV. The SRAM chip with normal function was fabricated and manually polished contac for SEPC inspection.
Notably, a FIB from FEI DB235 was used for cross-sectional inspection.
3.3 Results and discussion
3.3.1 SEPC result by primary electron energy adjustment
Two functional SRAM samples were polished to contact layer and the SEM image was acquired with 1 keV and 5 keV EPE, respectively. Figure 3-2 shows the SEM image with 1 keV EPE. In this image, the contrast of the contact can be classified into three levels. The contrast of the polysilicon contact, n+/p-well contact, and p+/n-well contact shows the low contrast, moderate contrast and high contrast, respectively. Figure 3-3 shows the SEM image obtained with 5 keV EPE. Contrast in the image also has three levels, but differs trend from that of Fig 3-2. The contrast of the polysilicon contact, n+/p-well contact, and p+/n-well contact shows the high contrast, low contrast and moderate contrast, respectively. Contrast with different EPE values behaves differently.
The SEPC arises from different surface potentials after primary electron (PE) irradiation.
The source of surface potential is the yield of the SE, which is not equal to that of the primary electrons. SE yield (δ) is the dividing of SE number by PE number. Figure 3-4 shows the tungsten SE yield (δ) as a function of EPE [24]. The surface potential will be positive charging when the SE yield is larger than 1, and negative charging when the SE yield is < 1. Based on Seiler’s study, the tungsten surface will be positive charging at EPE=1 keV and negative charging at EPE=5 keV [24].
Figure 3-5(a) is a schematic showing the contrast behavior when EPE is 1 keV. According to the traditional SEPC effect, when a sample was exposed to the 1 keV electron beam, a positive charge was generated on the sample surface. On a floating contact, such as a polysilicon contact, the positive charge remained on the surface, and reduced the number of SEs collected by the detector. Thus, the polysilicon contact has low contrast in the SEM image. For a positive charge, the p+/n-well is forward biased, such that the positive charge can be discharged through the p+/n-well to the substrate. Therefore, the p+/n-well contact will be in a higher contrast. Conversely, the n+/p-well is reverse biased for the positive charge. Thus, positive charges are seldom discharged through the n+/p-well to the substrate and remain on the surface of the contact connected to the n+/p-well, such that the contact on n+/p-well will be lower contrast. For the grounded contact, the positive charge will be discharged to the substrate, and will not reduce the number of SEs collected by the detector. Thus, the grounded
contact is brighter than the floating contact in the SEM image.
Figure 3-5(b) shows a schematic explaining contrast behavior when EPE is 5 keV. A negative charge will result on the sample surface (Fig. 3-3). Under this negative charging condition, the negative charge will be maintained on the polysilicon contact surface and the number of SEs collected by the detector will increase; the polysilicon contact is bright in the SEM image. For negative charging, the p+/n-well is reverse biased, and the negative charge cannot be discharged easily through the p+/n-well; thus, the p+/n-well contact will have high contrast. The n+/p-well contact is forward biased for the negative charge, such that the negative charge can be discharged through n+/p-well to the substrate. The n+/p-well contact will be low contrast in SEM image. For a grounded contact, the negative charge will be discharged to the ground and will not increase the number of SEs collected by the detector;
thus, the grounded contact is darker than the floating contact in the SEM image.
Table 3-1 summarizes the contrast behavior of contacts under the 1 keV and 5 keV EPE conditions. According to table 3-1, identifying the defective contact is easy when SEM images were acquired under both 1 keV and 5 keV.
3.3.2 Application of primary electron energy adjustment in defect isolation
The sample is a 0.15-µm SRAM chip that suffers a single bit failure. The sample is planar polished to Metal 1 layer for SEPC inspection to find any abnormality in the Metal 1
layer. Figure 3-6 shows the SEM image under 1 keV EPE. However, no abnormality was identified in the SEM micrograph. Thus, EPE was increased to 5 keV and another SEM micrograph was acquired, as shown in Fig. 3-7. One C-shaped Metal 1, which acts as the storage node of SRAM, is significantly brighter than the other C-shaped Metal 1. Thus, a cross-sectional inspection is performed by FIB, which reveals a porous n+/p-well contact in the failing cell, as shown in Fig. 3-8.
The abnormal SEPC from this sample cannot be identified at EPE=1 keV because three contacts are under Metal 1 layer: one connected to the p+/n-well another connected to the n+/p-well, and the last connected to polysilicon. When the sample is exposed to a 1 keV EPE condition, positive charges were generated on the sample surface. According to the principle of SEPC described previously, positive charges can be discharged by the contact connected to the p+/n-well. Thus, each Metal 1 can discharge its positive charges via its normal contact to the p+/n-well and all Metal 1 SEPC would be normally bright. In this case, the defect was an open contact connected to the n+/p-well. Therefore, one cannot detect this defect by EPE=1 keV. Conversely, negative charges will be generated on the sample surface when the sample is
The abnormal SEPC from this sample cannot be identified at EPE=1 keV because three contacts are under Metal 1 layer: one connected to the p+/n-well another connected to the n+/p-well, and the last connected to polysilicon. When the sample is exposed to a 1 keV EPE condition, positive charges were generated on the sample surface. According to the principle of SEPC described previously, positive charges can be discharged by the contact connected to the p+/n-well. Thus, each Metal 1 can discharge its positive charges via its normal contact to the p+/n-well and all Metal 1 SEPC would be normally bright. In this case, the defect was an open contact connected to the n+/p-well. Therefore, one cannot detect this defect by EPE=1 keV. Conversely, negative charges will be generated on the sample surface when the sample is