Chapter 1 Introduction
1.2 Overview of p/n diode
1.2.1 The formation of p/n diodes
The diode is the most essential part in modern solid-state devices and is widely utilized in light-emitting diodes (LEDs), solar cells, and VLSI devices. A diode is formed when p-type and n-type semiconductors are joined together. Figure 1-3(a) shows a band diagram of p-type and n-type semiconductors [7]. The major carriers in the p-type semiconductor are the holes and their Fermi level is close to the valance band. Conversely, the major carriers in an n-type semiconductor are the electrons and their Fermi level is close to the conduction band. When a p-type semiconductor and n-type semiconductor are joined together, these carriers start diffusing and combining. Finally, negative ions and positive ions are left on the p-type node and n-type node, respectively (Fig. 1-3(b) [7]. An electrical field is generated by these ions, which repels these carriers back to their original positions. The repelled current is called the drift current because the current drift is caused by the electrical field. When the diode reaches thermal equilibrium, drift current equals diffusion current and the Fermi level is a flat line across the diode.
This study examines the silicon (Si) p/n diodes manufactured using the VLSI process.
The diode is manufactured on a p-type (100) Si wafer with a resistivity of 8–12 Ohm-cm as the substrate. After shallow trench isolation (STI), phosphorous dopants were implanted into the Si wafer to form the n-well region and boron was implanted to form a p-well region. After
well formation, p+-type regions and n+-type regions were formed by boron implantation and arsenic implantation, respectively. Thermal activation at 1000°C for 5 s and metallization
were conducted sequentially.
1.2.2 Physical and electrical properties of p/n diode
Figure 1-4(a) shows the space charge distribution of a linearly graded junction; Fig.
1-4(b) shows the electrical field of the junction; Fig. 1-4(c) shows the electrical potential; and Fig 1-4(d) shows the band diagram of the junction [7]. The potential difference between the p node and n node, called built-in potential, is Vbi . Figure 1-5(a) shows the band diagram of a diode under thermal equilibrium [7]. Figure 1-5(b) shows the diode in the forward bias condition; the positive terminal of the battery is connected to the p node and the negative terminal is connected to the n node [7]. Under the forward bias condition, built-in potential is reduced to Vbi-VF, where VF is battery voltage. Because built-in potential is reduced to Vbi-VF, electrons in the n node and holes in the p node diffuse into the depletion region. Since major carriers are injected into the depletion region, depletion width will be reduced under the forward bias condition. The diffusion current from the major carrier is the current source of forward bias.
Figure 1-5(c) shows the diode under the reverse bias condition, in which the negative terminal of the battery is connected to the p node and the positive terminal is connected to the n node [7]. Under this reverse bias condition, the built-in potential is increased to Vbi+VR,
where VR is battery voltage. Because built-in potential increased to Vbi+VR, electrons in the n node and holes in the p node cannot diffuse into the depletion region. Since major carriers are repelled back to their original sites, depletion width increases under the reverse bias condition.
The drift current from the minor carrier is the current source of reverse bias and is small.
Figure 1-6 shows the current voltage characteristics of the diode [7]. Under the forward bias condition, electrons are injected into the n node and diffuse into the depletion region.
Holes are then injected into the p node and diffuse into the depletion region. Electrons and holes combine in the depletion region and complete the current flow in the entire circuit. Thus, current increases exponentially under the forward bias condition. Conversely, current under the reverse bias condition is drift current. Because drift current is contributed from minor carrier, it is small.
1.2.3 Applications of p/n diode
A diode is a basic component in solid-state devices and widely used in modern electronic devices. For instance, LEDs are essentially forward biased p-n diodes. Radiative recombination occurs when electrons and holes are injected across the diode junction. A photo detector is essentially a reverse bias p-n diode. Electrons and holes quickly drift in opposite directions under the influence of a strong electrical field. The diode is also a basic component in modern VLSI chips. The diode was placed in the reverse biased condition to transmit a signal for additional logical operations. The dopant distribution of a diode must be designed
such that device performance can be maximized. Figure 1-7 lists diode applications in LED and photo detector. [8].
1.3 Overview of very-large-scale integration (VLSI) chip 1.3.1 Logic VLSI chip
This work focuses on the complementary metal oxide semiconductor (CMOS) device.
The CMOS is constructed using the p channel MOSFET (PMOS) and n channel MOSFET (NMOS). Figure 1-8 is a schematic illustration of the cross-sectional structure of the CMOS;
the left side is an NMOS transistor and the right side is a PMOS transistor. The source side of the NMOS transistor connects to Vss. The drain site of the NMOS transistor pulls down to Vss level when the NMOS gate switches on. Conversely, the source side of the PMOS transistor connects to Vcc. The drain site of the PMOS transistor pulls up to Vcc level when the PMOS gate switches on; that is, the main function of the PMOS transistor is to transmit the Vcc signal and the NMOS transistor transmits the Vss signal. Thus, a CMOS chip transmits a Vss or Vcc signal through the logic operation of transistors. The advantage of CMOS technology is low power consumption. During their operating period, diodes remain in the reverse bias condition and consume energy only during the switching period.
The main function of a CMOS is to transmit a high or low signal through the logic operation. The components of the CMOS can be split into six nodes types—the n+/p-well node, NMOS gate node, p-well node, p+/n-well node, PMOS gate node, and n-well node.
From the perspective of electrical characteristics, the function of the NMOS gate node and PMOS gate node is similar; that is, each acts as a top plate of a capacitor and should resemble a high-resistance node. Thus, the NMOS gate node and PMOS gate node can be considered the same. The function of the p-well and n-well is to provide the source side of NMOS and PMOS transistors. The resistance of these two nodes is very low, such that they can be put into the same group before the manufacturing process is completed. For CMOS technology, CMOS components can be grouped into four node types—the n+/p-well node, gate node, p+/n-well node, and well node. The goal of defect isolation is to recognize these four nodes via a failure analysis process.
1.3.2 Static random access memory (SRAM)
SRAM is the memory that always stores the data in bit cells while chip power maintained. It does not need to re-write within a period, as does the dynamic random access memory (DRAM). Additionally, SRAM has the high-speed read and write capabilities and is adopted widely in central processing unit (CPU) chips. In modern integrated circuit (IC) manufacturing, SRAM is a leading product and the vehicle for advanced technology development [9]. However, the bit cell area of SRAM is larger than that of DRAM, meaning its manufacturing cost is higher.
A DRAM bit cell is composed of a transistor and capacitor. An SRAM bit cell is composed of six transistors—four NMOS transistors and two PMOS transistors. Figure 1-9(a)
shows the circuit of an SRAM bit cell. The role of PMOS transistors is to increase the signal to the Vcc level and is annotated as the pull up (PU) in the circuit. Conversely, the role of the NMOS transistor is to pull down the data to the Vss level, and is annotated as the pull down (PD) in the circuit. The PU and PD transistors are arranged in a latch circuit to retain data in the cell. The remaining NMOS transistors are called pass gate (PG) transistors, which control read and write timing. Figure 1-9(b) shows the layout pattern of the SRAM bit cell.
The failure mode of the SRAM bit can be identified via electrical testing. Since SRAM is a kind of CMOS chip, its power consumption is low while operating. Thus, the standby current (Isb) of SRAM should be low and this Isb will be tested at the start of the test process.
Even though electrical testing can locate the exact bit failure location, a further isolation process is still necessary for cause identification. Such a failure analysis procedure includes using SEPC to isolate any possible high resistance or gate oxide rupture in a bit cell. If no abnormality were found via SEPC analysis, a nano probe tool is applied to measure the electrical performance of transistors [10].
1.3.3 Lateral double diffused metal oxide semiconductor (LDMOS)
According to Moore’s law, the transistor counts will double every 1.8 years. The dimensions of transistors must also decrease according to this law. With the scalability and cost savings for manufacturing, CMOS technology is widely used for digital circuits.
However, the world remains analog. Digital processing should be converted back to analog
efficiently. Thus, the lateral double diffused metal oxide semiconductors (LDMOSs) were developed to reduce manufacturing costs and increase flexibility in high-voltage and high-current applications (e.g., power management ICs, displays, motor drivers, and class-D amplifiers) [11,12,13].
Figure 1-10 shows the cross-sectional structure of the lateral double diffused negative metal oxide semiconductors (LDNMOSs) [13]. In this cross section, the n-well was used as the extended drain side to sustain high power and the p-well was the body site of the device.
Channel length, Lchannel, is the area where the p-well and poly gate overlap, and is controlled by the physical locations of the active area, the poly gate, n-well, and p-well. In this work, the mismatch mechanism of a current mirror composed of lateral double diffused positive metal oxide semiconductors (LDPMOSs) is investigated via in situ SEPC inspection. The SEPC inspection method identified a misaligned p-well mask, causing Lchannel variation and deviation of transistor saturation current from the target value.
1.4 Overview of defect isolation by SEPC
As the dimensions of transistors are scaling, the demand for an inspection tool with good spatial resolution has increased. Moreover, the transistor number of a VLSI containsbillion of transistors, indicating that this inspection tool should be able to analyze as many transistors as possible. With the improvements of electron guns and reduction of aberrations, SEM image resolution has improved to the nm scale and with a large view field. Additionally, the
secondary electron in SEM is sensitive to the voltage distribution of the inspected surface, facilitating inspection of high-resistance defects on ICs [14-16]. The contrast phenomenon arises from the influence of surface potential, and is called SEPC, or voltage contrast (VC) [17].
The SEPC effect was first observed in 1941 by Knoll [18]. Hardy et al. characterized SEPC with a voltage precision of 50 mV in the range of -30–30 V [19]. Aton et al. and Manhant-Shetti et al. demonstrated that standard SEM can isolate continuity failure of a special IC test pattern [20, 21]. The detection limit was 2 × 1011 Ohm [21]. Sakai et al. biased the test pattern to lower the detection limit to 1 × 104 Ohm [22]. Colvin utilized SEPC to isolate gate oxide leakage [23]. The SEPC arises from surface potential after electron beam irradiation [24]. This method has a contactless capability in voltage investigations and has been adopted for IC debugging [25].
1.5 Overview of dopant profiling by SEPC
Modern microelectronic IC technology enhances the performance of transistor through scaling down of transistor [5, 6]. The distribution and concentration of dopant is the key to enhance device performance when developing nano-scale devices. With a sensitivity from 1016 to 1020 cm-3 and a spatial resolution of 10 nm, the SEPC effect in SEM has emerged as the potential method for dopant profiling [26, 27]. In addition, SEPC arise from the built-in potential across the diode, indicating this is an electrical measurement method which collects
active dopant signal only [27].
The dopant contrast in SEM was first observed in 1967 by Change and Nixon [28]. After that, researchers have been investigating the dopant contrast mechanism and each group has proposed its own proposal. Pervoaic et al. and Turan et al. proposed that surface potential determines secondary electron emission rate [29, 30]. Sealy et al. and Muzzo et al proposed that a patch field outside the specimen is a major factor in dopant contrast [31, 32]. Figure 1-11 shows the simulation result that the built in potential initiates an electrical field outside the specimen [32]. The electrical field will repel electron out the p-type node, but attract electron back to specimen in n-type node, resulting the brightness and darkness contrast in p type node and n type node, respectively. Hsiao et al. observed that the strain effects will influence dopant contrast [33]. Elliott et al. and Venables et al. reported that the SEPC profile of a p+/n-well junction shows a linear relationship with the logarithm of the SIMS depth profile and their results are shown in Figure 1-12 [26, 27]. SIMS is a dopant profiling tool by collecting the all dopant elements no matter is it an active dopant or not. Figure 1-13 shows the Elliott’s study on a biased junction [27]. Elliot found that the SEPC intensity is proportional to the biased voltage, indicating the surface potential determines the secondary electron emission rate [27].
1.6 Overview of dopant profiling techniques 1.6.1 Secondary ion mass spectrometry (SIMS)
SIMS is an analytical tool with high sensitivity and a wide dynamic detection range. The tool sputters the specimen surface using a primary ion beam and measures the elements using a mass spectrometer. The SIMS detection limit is 1012–1016 cm-3, and depends on material type [34]. With careful calibration of sputtering rate and low primary ion energy, SIMS has been used widely to characterize the depth profile of shallow junctions in CMOS devices [35].
However, SIMS is a destructive analytical method that depicts the dopant profile by sputtering the analytical target to mass spectrometer. All sputtered elements will be guided to the mass spectrometer and counted in the depth profile. Target dimensions should be larger than 50 × 50 µm, meaning that SIMS cannot be applied in the site-specific real circuit.
1.6.2 Scanning capacitance microscope (SCM)
SCM is a scanning probe microscope that uses a tiny tip to scan a specimen and record the capacitance response. Williams conducted the two-dimensional dopant profiling via SCM with a 10 nm spatial resolution [36]. A high-quality oxide should be grown in a specimen’s surface for reliable measurement, making the repeatability of SCM poor for many samples.
Figure 1-14 shows schematic to illustrate the SCM operation principle [36].
1.6.3 Kelvin force probe microscope (KFPM)
KFPM combines AFM and SCM to map the electrostatic voltage difference between the tip and specimen surfaces [37]. The electrostatic force between the tip and specimen under a constant range, Z, is given by
dZ
F =1/2dC V2……….(1)
where C is coupling capacitance and V is electrostatic voltage between the tip and specimen [37]. Surface potential is determined as measured electrical force, coupling capacitance, and tip potential. Figure 1-15 shows the KFPM system [37].
1.6.4 Electron holography
Electron holography is also a surface potential mapping method that uses interference of an off-axis electron beam in transmission electron microscope (TEM) [38]. With improved spherical aberration and a field emission gun, Griyelyuk et al. reported a 2D diode potential mapping with a spatial resolution of 6 nm and voltage sensitivity of 0.17 V [39]. However, an accurate potential map requires a sample with uniform thickness, such that electron holography is rarely used in IC manufacturing.
1.6.5 Chemical delineation
Chemical delineation uses acids to etch heavily doped areas selectively [40]. The silicon surface is first oxidized to silicon dioxide (SiO2) by nitric acid and then dissolved into a solution by fluride acid. The etching rate is limited by the concentration of holes in the sample surface [41]. The etching rate of n+ Si can be enhanced by band bending in solution, accumulating holes in the n+ surface. The etching rate of p+ silicon can be enhanced by anodic biasing, creating holes in the p+ surface [42]. However, this method has difficulty identifying the precise well profile due to low dopant dosages. Further, wet etching methods are
destructive, meaning that the doping area will be etched out permanently.
1.7 Motivations of study
Transistors are built with solid materials and using their semiconductor electrical properties to perform complex computations. SEM has been widely used to inspect physical and electrical transistor properties. For instance, people use the secondary electron (SE) to measure transistor dimensions, use the backscattered electron (BSE) to inspect element contrast, and use the Auger electron and X-rays for element analysis. The SE contrast, which arises from the differences in surface potential, is called SE potential contrast (SEPC) and can be used to inspect electrical transistor properties. The SEPC has been widely applied in electrical defect isolation and dopant profiling.
Even though experimental results demonstrate that SEPC is an efficient method for continuity failure isolation, failure mode of an IC is not just a continuity issue. Four node types are used in VLSI chips, polysilicon gate node, n+/p-well node, p+/n-well node, and well nodes [43]. The traditional SEPC method cannot distinguish between all node types. This study investigates the SEPC by varying primary electron energy and discusses the source of potential contrast without additional biasing. Finally, this study offers a procedure to distinguish between different nodes in a chip.
In application of dopant profiling, many studies have applied SEPC for electrically active dopant profile mapping [31, 32]. However, as the device has nano-scale dimensions, the study
of SEPC in real circuit is rarely reported. The spatial resolution, site-specific analytical capability and poor SEPC signal in small bandgap material are emerging as the top three issues in SEPC method [44, 45]. Jepson et al. observed that the SEPC spatial resolution is improved in helium ion microscopy (HeIM) [46, 47]. Kazemian et al study of using focused ion beam (FIB) on sample preparation to meet the requirements for site-specific analysis [48].
However the SEPC is significantly reduced due to the damage layer generated by FIB, as shown in Figure 1-16 [48]. Hence, this study fills the gap in the literature by enhancing dopant contrast with nano-probe assistance. In addition, author converts the SEPC image to a voltage scale and elucidates theoretical description about the device physics [49-51].
1.8 Organization of the thesis
In chapter 1, the CMOS technology revolutions and process characterization challenges are introduced. We also have brief overview of the physical and electrical properties of the pn diode. The applications of CMOS technology in the logic circuit, SRAM, and LDMOS are also addressed in chapter 1. Additionally, the overview of defect isolation and dopant profiling using SEPC, and techniques for dopant profiling are also summarized in chapter 1. In chapter 2, the experimental instruments, sample preparation methods, electrical and physical characterization techniques are presented. This chapter introduces the secondary electron in SEM, sample milling tool FIB, electrical measurement tool nano-probe system and AFM.
In chapter 3, the SEPC effect with varying primary electron beam energy is investigated.
A procedure is suggested to distinguish all node types in chip. Finally, this new procedure is applied in a real case and isolates defect successfully. Next, in chapter 4, the sample preparation methods for SEPC in dopant contrast inspection are examined. And a application
A procedure is suggested to distinguish all node types in chip. Finally, this new procedure is applied in a real case and isolates defect successfully. Next, in chapter 4, the sample preparation methods for SEPC in dopant contrast inspection are examined. And a application