Summary

In summary, the SEPC exhibits different contrast effects by adjusting the primary electron energy. The proposed SEPC procedure can distinguish between all contact types in an SRAM chip, overcoming the weakness of traditional SEPC. The SEPC images under varying primary electron energies were acquired experimentally and discussed. The surface-charging model explained the contrast behavior well. Finally, the proposed SEPC procedure was applied to isolate a porous n⁺/p-well contact, which cannot be found via the tradition SEPC method.

Figure 3-1 Sketch illustrates the function of E×B filter. Secondary electron (SE) is with low energy and could be guided to the upper detector by E×B filter..

Figure 3-2 The SEPC image of contacts from a 0.15 µm SRAM with 1 keV EPE.

Figure 3-3 The SEPC image of contacts from a 0.15 µm SRAM with 5 keV EPE.

Figure 3-4 The schematic curve shows secondary electron yield (δ) as a function of EPE for tungsten.[9]

Figure 3-5 (a)Schematic illustrates the SEPC effect under 1 keV EPE. (b)Schematic illustrates the SEPC effect under 5 keV EPE.

Figure 3-6 The SEPC image of metal 1 from a 0.15 µm SRAM with 1 keV EPE.

Figure 3-7 The SEPC image of metal 1 from a 0.15 µm SRAM with 5 keV EPE.

Figure 3-8 The cross-section image shows porous contact in n⁺/p-well node by FIB sample preparation.

Table 3-1 Summary of the contrast behavior of contacts under the 1 keV and 5 keV EPE conditions.

Chapter 4

Junction profiling and junction leakage isolation by SEPC

4.1 Introduction

Developments in microelectronic integrated circuit technology shrink transistor dimensions to increase device performance. The scaling down of semiconductor devices was initially achieved by simply reducing the physical width of the wells. The first issue related to downscaling the physical well width is controlling photomask alignment and dimension uniformity [44, 45]. Poor control can create unwanted leakage paths. Numerous reports have described how to inspect the distribution of implanted dopant profiles in junctions, for instance, chemical delineation uses nitric and fluride acids to selectively etch the heavily doped areas [63]. However, this method has difficulty revealing the precise well profile due to low dosage of the dopants. In addition, wet etching methods are destructive, meaning that the doping area will be etched out permanently. Other methods such as secondary ion mass spectrometry and scanning capacitance microscoprope could work for dopant profile inspection, but they provide insufficient spatial resolution for small areas [64, 65].

In the chapter 3, author introduces a new SEPC procedure to isolate the defects happen in contact and metal layers. Recently, secondary electron potential contrast (SEPC) using

scanning electron microscope (SEM) also demonstrated a strong applicability to dopant profile imaging [26, 27]. The SEPC signals arise from differences in the built-in potential between different doping areas. Since this inspection method uses the built-in potential of a diode, it affords a non-destructive approach to doping inspection. Numerous publications have conducted studies on materials with wide energy bandgaps, such as SiC [32]; however, SEPC signal inspection is more difficult with silicon having a small band gap energy of 1.1 eV. The damaged layer generated by sample preparation method is also an important factor for dopant inspection. In this chapter, we study three methods of sample preparation and provide optimum condition for dopant inspection. Second we illustrate SEPC inspection of silicon p⁺/n-well junctions and also develops a dynamic trigger for isolating p⁺/n-well junction leakage.

4.2 Experimental details

A SE is generated by the inelastic collision between the primary electron beam and substrate. The energy of the SE is <50 eV and escape depth is <40 nm [48]. Kazmianm et al.

demonstrated that the sample preparation procedure is a critical factor for dopant contrast [48].

Thus, before conducting the SEPC experiment, three different sample preparation methods are investigated. The experiment uses a Hitachi SEM S4700. With its good through-the-lens SE detector, the SE image contrast of different dopants is both sharp and clear. This study also utilized a standard SEM operating condition to view SEPC images using different methods.

That is, accelerating voltage is 1 keV and emission current is 15 uA. In this study, 0.22 µm and 0.15 µm logic chips were used as examples. Three methods were applied to prepare samples for dopant contrast inspection on doped silicon regions. These methods are manual polishing, Ar-sputtering, and wet solution etching. Significant contrast is clear on freshly cleaved doped silicon, and contrast is enhanced after a NH₄F chemical treatment [53]. This removes the oxide layer and passivates the surface by saturating dangling bonds with hydrogen [53]. The primary goal is to change the state of the silicon surface. Ammonium fluoride solution (5 grams of NH₄F crystals in 30ml water) was selected because it produces an atomically flat surface compared with aqueous HF acid, which is more commonly used [66]. In this study, bare silicon samples were dipped in NH₄F solution and inspected by SEM.

After the identification of the optimum sample preparation method, we adopted these experiences in a real case, in which a SRAM suffers high standby current failure. The specimen in this study was a static random access memory (SRAM) that was manufactured using 0.11 µm IC technology. A p-type (100) silicon wafer with a resistivity of 8–12 Ohm-cm served as the substrate. After shallow trench isolation (STI), phosphorous dopants were implanted with a dosage of 2.6 × 10¹³ ions-cm⁻² and an ion energy of 150 keV into the silicon wafer to form the p-well, while boron implantation was carried out to form a p-well region with a dosage of 3.0 × 10¹³ ions-cm⁻² and an ion energy of 160 keV. After the well formation process, p⁺-type source and drain regions were formed by boron implantation with a dosage of

1.5 × 10¹⁵ ions-cm⁻² and ion energy of 5 keV. Thermal activation at 1000°C for 5 s and metallization were carried out sequentially as formal procedures. The sample was plane polished to the contact layer for conductive atomic force microscope (C-AFM) measurements.

The sample was manually polished to the cross section site of interest for cross sectional SEPC inspection. A Hitachi S4700, equipped with a through-the-lens E×B detector, was the major tool for SEPC inspection. An optimum SEM operation conditions were set to view the image of the diode. The secondary electron comes from an inelastic collision between the primary electron and the inner shell electron. The energy of the secondary electron is typically smaller than 50 eV. It is well known that the built-in potential of a diode can be expressed as a function of dopant concentrations:

)

where k is the Boltzmann constant, T is the absolute temperature, q is the elementary charge, and N_a and N_d are the concentration of the acceptors and donors, respectively. N_i is the intrinsic carrier concentration of silicon. For silicon, the maximum built-in potential is equal to its band gap energy of 1.1 eV.

4.3 Results and discussion

4.3.1 Comparison of sample preparation methods for SEPC inspection

Manual polishing removes the layer above the silicon. An NH₄F dip is then the most

convenient and easy method for removing the rest of the layer on the silicon surface. However, identifying a precise position in a chip is difficult. Without careful inspection, over-polishing or under-polishing may lead to failed sample preparation. Further, the repeatability of manual polishing is poor. Figure 4-1 shows the manual polishing result.

After removing the layers above the doped silicon, Ar sputtering was used to change the state of the silicon surface. The Ar-sputtering uses a Gatan Model 693 to bombard the silicon surface, slightly damaging the implant region. This method produces the poorest SEPC results.

Figure 4-2 only shows the n/p well contrast; implant details are not observed.

The final method uses HF acid to remove all layers above the silicon before dipping the specimen into the NH₄F solution to change the state of the silicon surface. The primary advantage of wet solution etching is convenience; that is, etching is easily performed and generates excellent results. However, the most important advantages are its large sample size and repeatability. Figure 4-3 shows the sample preparation result, in which n⁺, p⁺, n-well, and p-well is observed clearly. Table 4-1 summarizes the sample preparation result. Pure wet solution is with the best sample preparation result in dopant region, repeatability, and inspection area.

4.3.2 Junction leakage isolation by SEPC

After identification of sample preparation method, this work studies an SRAM high standby current failure due to junction leakage. Figure 4-4(a) depicts the electrical

characteristics of tip current versus substrate voltage for leaky and non-leaky p⁺/n-well contact regions by C-AFM. The leaky contact suffered early breakdown in its reverse bias region. Figure 4-4(b) shows a current map of the SRAM chip under C-AFM. The map indicates that the contacts standing on the p⁺/n-well exhibited abnormal leakage. The leaky contacts appeared in alternative rows. A misalignment during the manufacture of well region contacts was suspected to be the cause of the leakage.

Figure 4-5 shows a cross sectional SEPC inspection of the p⁺/n-well region, and shows a clear and sharp interface between the p- and n-wells. The p-well image is bright, and the n-well is dark. In this case, the p-well was shifted a little to the right. In a properly aligned p⁺/n-well region, the brighter image of the p⁺ contact area would be situated on the darker n-well area. However, a p⁺ contact region with a leaky contact on the left side is invisible because the leaky p⁺/n-well has the same contrast as the n-well. No obvious interface was observed between the p⁺ and n-well in the leaky area. In this study, the SEPC technology directly revealed evidence of p⁺/n-well junction leakage originating from a short to the p⁺ contact area, due to misalignment of the p-well. Applying a negative bias to the p-well region can extend the width of the depletion region between the n- and p-well—eliminating the leakage path from p⁺ to the adjacent p-well and returning the electrical operation of the p⁺/n-well junction to normal. Figure 4-6 shows the potential contrast when applying a bias of

−1.8 V to the substrate. The image of the leaky p⁺ junction reappeared, which means that the

p⁺/n-well will work normally—the negative bias eliminated the leakage path.

The formation of leaky paths due to the p-well misalignment, as well as the effect of negative bias trigger can be illustrated as follows. A misalignment of the p-well region to the right caused the p-type dopant to be implanted in the sidewall of the STI structure, producing a leakage path that passed through the p⁺ region to the STI sidewall. As shown in Fig. 4-7, the leakage path passed through the p⁺ contact region to the adjacent p-well. SEPC inspection conducted with a floating p-well substrate showed that the depletion width was small.

Applying a negative bias of −1.8 V to the p-well increased the depletion area width and pinched off the leakage path from the p⁺ region to p-well, as shown in Fig. 4-8. Since this cut off the leakage path, the image of the leaky p⁺ region reappeared in the SEPC inspection.

Therefore, the proposed in situ dynamic trigger effectively isolated the p⁺/n-well junction leakage, allowing the junction to operate normally.

4.4 Summaries

In summary, secondary electron potential contrast proves to be an excellent method for profiling 2D junctions of silicon devices—it can characterize the leakage mechanism in a p⁺/n-well junction. A misalignment of p-wells was identified as the root cause of junction leakage and, in this case, negative substrate biasing created an extended depletion width that eliminated the leakage path. The potential contrast of the leaky p⁺/n-well reappeared and normal operation returned. The experimental results demonstrate that in-situ biasing offers a

promising and effective approach to investigating device physics of a diode.

Figure 4-1 The SEPC image of the manual polishing result.

Figure 4-2 The SEPC image of the Ar sputter result.

Figure 4-3 The SEPC image of the wet etching result.

Table 4-1 Summaries of capability in dopant contrast, repeatability, and inspection area between sample preparation methods.

Figure 4-4 (a) Characteristics of tip current versus substrate voltage for the leaky and non-leaky P⁺/N-well contacts. (b) A current map of a SRAM chip under conductive atomic force microscope.

Figure 4-5 An SEPC image of the P⁺/N-well diode with a floating substrate.

The inset shown in the upper right corner is a schematic cross section. The P-well is shifted a little to the right. A P⁺ region with a leaky contact on the left side is not observed, while the image of a non-leaky P⁺ contact region on the right is observed clearly.

Figure 4-6 SEPC image of the P⁺/N-well diode with a substrate bias of −1.8V.

The inset is a schematic cross section. The previous missing image of P⁺ region with leaky contact is clearly seen.

Figure 4-7 Schematic to demonstrate leakage behavior of the P⁺/N-well diode with a floating substrate.

Figure 4-8 Schematic of a P⁺/N-well diode with a substrate bias of −1.8V to demonstrate an extended depletion region for eliminating the leakage path from P⁺ to the adjacent P-well.

Chapter 5

Junction profiling by SEPC with in-situ nano-probe biasing

5.1 Introduction

Semiconductor transistor performance is determined by the dopant distribution and concentration [5, 6]. The 2-D junction profile technique has become a vital issue when developing nano-scale devices. Many studies have been developed to investigate junction profile, include secondary ion mass spectrometry (SIMS) [65], chemical delineation [67, 68], scanning capacitance microscope (SCM) [64], Kelvin force probe microscope (KFPM) [37], and electron holography [38, 39]. Secondary ion mass spectrometry (SIMS) is extensively used to obtain dopant profiles with effective quantization. However, this method provides only 1-D information on specific test key structure [64, 65].Chemical delineation using acid solutions can yield 2-D dopant profiles in the active region where the implant dosage is high [40, 69, 42]. This method, however, cannot easily inspect the dopant profile of a well region clearly because it uses low dopant dosage. SCM is another popular method for acquiring a 2-D dopant profile. A high-quality oxide layer must be grown on silicon wafers to enable a reliable quantitative measurement, increasing the complexity of the SCM. KFPM and electron holography depict the junction profile through surface potential mapping [37-39]. The KFPM uses a tiny probe to scan across the junction and gather the long range electrostatic potential

interaction between the probe and specimen surface [37]. Off-axis electron holography reconstructs the electrostatic potential distribution across a diode based on electron interference [38, 39].

Recently, researchers have proposed the use of secondary electron potential contrast (SEPC) to inspect junction profile, with a sensitivity from 10¹⁶ to 10²⁰ cm^-3 and a spatial resolution of 10 nm [26, 27, 49, 70, 71]. Since 1967, researchers have been investigating the mechanism of dopant contrast in scanning electron microscope (SEM). Various groups of researchers have studied factors that influence of dopant contrast; each group has proposed its own proposal. For example, Pervoaic et al. and Turan et al. proposed that surface potential determines secondary electron emission rate [29, 30]. Sealy et al. proposed that a three-dimensional field outside the specimen is a major factor in dopant contrast [31]. Hsiao et al. studied strain effects in dopant contrast enhancement [33]. Elliott et al. and Venables et

al. reported that the SEPC profile of a p⁺/n-well junction shows a linear relationship with the logarithm of the SIMS depth profile [26, 27]. Elliott’s study on a biased junction found that the SEPC intensity is proportional to the built-in voltage [27]. However, when the device of interest has nano-scale dimensions, spatial resolution, site-specific analytical capability and SEPC signal enhancement are the three most important issues in SEPC method [44, 45].

Jepson et al. observed that the SEPC spatial resolution is improved in helium ion microscopy (HeIM), in which a probe size as small as 0.25 nm can be used, making HeIM an ideal

candidate for nano-scale dopant mapping in the future [46, 47]. Kazemian et al. proposed the preparation of a sample using a focused ion beam (FIB) to meet the requirements for site-specific analysis [48].

Even though the above studies show that SEPC is a promising technique for junction profiling. However, applications of SEPC in junction profiling of actual circuits are rarely reported, probably because SEPC is difficult to observe in site-specific locations due to the reduced SEPC signals under standard SEM conditions. Sealy et al. suggested that surface band bending on a cleaved diode will reduce the dopant contrast [31]. Recent site-specific studies suggest that FIB sample preparation may indeed facilitate dopant contrast inspection [48]. During sample preparation, however, damage to the surface layer can reportedly reduce dopant contrast [48]. Additionally, the SEPC signal arises from the built-in potential across the diode. The drop in SEPC signal reduction is expected to be even worse for semiconductors with a smaller bandgap energy. In the worst case, SEPC cannot be observed by SEM imaging [50]. Hence, this study fills the gap in the literature by investigating solutions for enhancing dopant contrast by in situ bias of the diode with nano-probe tips. The specific aims of this report are (a) to enhance dopant contrast with nano-probe assistance, (b) to link the image contrast to a voltage scale, and (c) to elucidate theoretical assumptions about the device physics. The proposed solution may also serve as a basis for further studies of SEPC mechanisms with static triggers. The simplicity of the method should enable

widespread adoption in dopant profile inspection.

5.2 Experimental details

In this experiment, a static random access memory (SRAM) cell was manufactured for junction study. The experimental specimen was a functional static random access memory (SRAM) module manufactured with 90 nm IC technology. A p-type (100) silicon wafer with 8-12 Ohm-cm resistivity served as the substrate. After patterning the active area, implantation

procedures were performed to form the well regions and the plus regions. Thermal activation at 1000°C for 5 s and metallization were carried out sequentially as formal procedures. A

SRAM chip with normal function was fabricated and manually polished to enable cross-sectional observation of the site of interest by SEM.

All SEM images in this paper were obtained with a Hitachi S4800 equipped with an E×B filter. The E×B filter removes the high energy tail of the backscattered electron (BSE) and guides SE to the upper detector to enhance the SEPC effect on the silicon. The SEM operating conditions were optimized for visualizing the diode. The SEPC image was obtained using an accelerating energy of 1 keV and a working distance of 6 mm. Although the SEPC image was enhanced by the E×B detector, surface band bending and damaged surface layer could reduce SEPC and limit its application in real circuit. To minimize the contrast reduction effect from these factors, a nano-probe system was installed in the SEM chamber. The junction condition was reverse biased with a four-micromanipulator nano-probe system mounted to the Hitachi

S4800 stage. The nano-probe tip had a 50 nm radius and could probe any node found in the SEM image. Figure 5-1 illustrates a single probe biasing proposal applying on a partial cross section of the SRAM chip to schematically illustrate the SEPC inspection procedure. Three p⁺/n-well junctions, two polycrystalline Si gates, and a nano-probe tip probe in the middle of a p⁺/n-well node are shown in the Fig. 5-1. The middle p⁺/n-well node serves as a Vss node of SRAM and connects to n-well through metal routing. The other two p⁺/n-well nodes serve as the drain node of SRAM. The middle p⁺/n-well junction was electrically biased with a trigger voltage 1 V. The p-substrate was kept on the ground state. The colors of the left and right p⁺/n-well junctions and p-substrate illustrate the dopant contrast after electricity was biased.

Figure 5-2 shows a partial cross-section of the SRAM chip with a pair of nanoprobing tips was inserted on the right-most p⁺/n-well junction, in which an green color represents the SEPC signal when the probe tips were electrically biased with a trigger voltage of -1 V on the

Figure 5-2 shows a partial cross-section of the SRAM chip with a pair of nanoprobing tips was inserted on the right-most p⁺/n-well junction, in which an green color represents the SEPC signal when the probe tips were electrically biased with a trigger voltage of -1 V on the