Summaries

In summary, secondary electron potential contrast proves to be an excellent method for profiling 2D junctions of silicon devices—it can characterize the leakage mechanism in a p⁺/n-well junction. A misalignment of p-wells was identified as the root cause of junction leakage and, in this case, negative substrate biasing created an extended depletion width that eliminated the leakage path. The potential contrast of the leaky p⁺/n-well reappeared and normal operation returned. The experimental results demonstrate that in-situ biasing offers a

promising and effective approach to investigating device physics of a diode.

Figure 4-1 The SEPC image of the manual polishing result.

Figure 4-2 The SEPC image of the Ar sputter result.

Figure 4-3 The SEPC image of the wet etching result.

Table 4-1 Summaries of capability in dopant contrast, repeatability, and inspection area between sample preparation methods.

Figure 4-4 (a) Characteristics of tip current versus substrate voltage for the leaky and non-leaky P⁺/N-well contacts. (b) A current map of a SRAM chip under conductive atomic force microscope.

Figure 4-5 An SEPC image of the P⁺/N-well diode with a floating substrate.

The inset shown in the upper right corner is a schematic cross section. The P-well is shifted a little to the right. A P⁺ region with a leaky contact on the left side is not observed, while the image of a non-leaky P⁺ contact region on the right is observed clearly.

Figure 4-6 SEPC image of the P⁺/N-well diode with a substrate bias of −1.8V.

The inset is a schematic cross section. The previous missing image of P⁺ region with leaky contact is clearly seen.

Figure 4-7 Schematic to demonstrate leakage behavior of the P⁺/N-well diode with a floating substrate.

Figure 4-8 Schematic of a P⁺/N-well diode with a substrate bias of −1.8V to demonstrate an extended depletion region for eliminating the leakage path from P⁺ to the adjacent P-well.

Chapter 5

Junction profiling by SEPC with in-situ nano-probe biasing

5.1 Introduction

Semiconductor transistor performance is determined by the dopant distribution and concentration [5, 6]. The 2-D junction profile technique has become a vital issue when developing nano-scale devices. Many studies have been developed to investigate junction profile, include secondary ion mass spectrometry (SIMS) [65], chemical delineation [67, 68], scanning capacitance microscope (SCM) [64], Kelvin force probe microscope (KFPM) [37], and electron holography [38, 39]. Secondary ion mass spectrometry (SIMS) is extensively used to obtain dopant profiles with effective quantization. However, this method provides only 1-D information on specific test key structure [64, 65].Chemical delineation using acid solutions can yield 2-D dopant profiles in the active region where the implant dosage is high [40, 69, 42]. This method, however, cannot easily inspect the dopant profile of a well region clearly because it uses low dopant dosage. SCM is another popular method for acquiring a 2-D dopant profile. A high-quality oxide layer must be grown on silicon wafers to enable a reliable quantitative measurement, increasing the complexity of the SCM. KFPM and electron holography depict the junction profile through surface potential mapping [37-39]. The KFPM uses a tiny probe to scan across the junction and gather the long range electrostatic potential

interaction between the probe and specimen surface [37]. Off-axis electron holography reconstructs the electrostatic potential distribution across a diode based on electron interference [38, 39].

Recently, researchers have proposed the use of secondary electron potential contrast (SEPC) to inspect junction profile, with a sensitivity from 10¹⁶ to 10²⁰ cm^-3 and a spatial resolution of 10 nm [26, 27, 49, 70, 71]. Since 1967, researchers have been investigating the mechanism of dopant contrast in scanning electron microscope (SEM). Various groups of researchers have studied factors that influence of dopant contrast; each group has proposed its own proposal. For example, Pervoaic et al. and Turan et al. proposed that surface potential determines secondary electron emission rate [29, 30]. Sealy et al. proposed that a three-dimensional field outside the specimen is a major factor in dopant contrast [31]. Hsiao et al. studied strain effects in dopant contrast enhancement [33]. Elliott et al. and Venables et

al. reported that the SEPC profile of a p⁺/n-well junction shows a linear relationship with the logarithm of the SIMS depth profile [26, 27]. Elliott’s study on a biased junction found that the SEPC intensity is proportional to the built-in voltage [27]. However, when the device of interest has nano-scale dimensions, spatial resolution, site-specific analytical capability and SEPC signal enhancement are the three most important issues in SEPC method [44, 45].

Jepson et al. observed that the SEPC spatial resolution is improved in helium ion microscopy (HeIM), in which a probe size as small as 0.25 nm can be used, making HeIM an ideal

candidate for nano-scale dopant mapping in the future [46, 47]. Kazemian et al. proposed the preparation of a sample using a focused ion beam (FIB) to meet the requirements for site-specific analysis [48].

Even though the above studies show that SEPC is a promising technique for junction profiling. However, applications of SEPC in junction profiling of actual circuits are rarely reported, probably because SEPC is difficult to observe in site-specific locations due to the reduced SEPC signals under standard SEM conditions. Sealy et al. suggested that surface band bending on a cleaved diode will reduce the dopant contrast [31]. Recent site-specific studies suggest that FIB sample preparation may indeed facilitate dopant contrast inspection [48]. During sample preparation, however, damage to the surface layer can reportedly reduce dopant contrast [48]. Additionally, the SEPC signal arises from the built-in potential across the diode. The drop in SEPC signal reduction is expected to be even worse for semiconductors with a smaller bandgap energy. In the worst case, SEPC cannot be observed by SEM imaging [50]. Hence, this study fills the gap in the literature by investigating solutions for enhancing dopant contrast by in situ bias of the diode with nano-probe tips. The specific aims of this report are (a) to enhance dopant contrast with nano-probe assistance, (b) to link the image contrast to a voltage scale, and (c) to elucidate theoretical assumptions about the device physics. The proposed solution may also serve as a basis for further studies of SEPC mechanisms with static triggers. The simplicity of the method should enable

widespread adoption in dopant profile inspection.

5.2 Experimental details

In this experiment, a static random access memory (SRAM) cell was manufactured for junction study. The experimental specimen was a functional static random access memory (SRAM) module manufactured with 90 nm IC technology. A p-type (100) silicon wafer with 8-12 Ohm-cm resistivity served as the substrate. After patterning the active area, implantation

procedures were performed to form the well regions and the plus regions. Thermal activation at 1000°C for 5 s and metallization were carried out sequentially as formal procedures. A

SRAM chip with normal function was fabricated and manually polished to enable cross-sectional observation of the site of interest by SEM.

All SEM images in this paper were obtained with a Hitachi S4800 equipped with an E×B filter. The E×B filter removes the high energy tail of the backscattered electron (BSE) and guides SE to the upper detector to enhance the SEPC effect on the silicon. The SEM operating conditions were optimized for visualizing the diode. The SEPC image was obtained using an accelerating energy of 1 keV and a working distance of 6 mm. Although the SEPC image was enhanced by the E×B detector, surface band bending and damaged surface layer could reduce SEPC and limit its application in real circuit. To minimize the contrast reduction effect from these factors, a nano-probe system was installed in the SEM chamber. The junction condition was reverse biased with a four-micromanipulator nano-probe system mounted to the Hitachi

S4800 stage. The nano-probe tip had a 50 nm radius and could probe any node found in the SEM image. Figure 5-1 illustrates a single probe biasing proposal applying on a partial cross section of the SRAM chip to schematically illustrate the SEPC inspection procedure. Three p⁺/n-well junctions, two polycrystalline Si gates, and a nano-probe tip probe in the middle of a p⁺/n-well node are shown in the Fig. 5-1. The middle p⁺/n-well node serves as a Vss node of SRAM and connects to n-well through metal routing. The other two p⁺/n-well nodes serve as the drain node of SRAM. The middle p⁺/n-well junction was electrically biased with a trigger voltage 1 V. The p-substrate was kept on the ground state. The colors of the left and right p⁺/n-well junctions and p-substrate illustrate the dopant contrast after electricity was biased.

Figure 5-2 shows a partial cross-section of the SRAM chip with a pair of nanoprobing tips was inserted on the right-most p⁺/n-well junction, in which an green color represents the SEPC signal when the probe tips were electrically biased with a trigger voltage of -1 V on the p⁺ side and 0 V on the n-well side.

5.3 Results and discussion

5.3.1 p+/n-well Junction Profile with Single Nano-probe Biasing

Figure 5-3 shows an SEM image that corresponds to Fig. 5-1, in which nano-probe tip applied to the middle p⁺/n-well node with positive 1 V and the p-substrate with ground.

Because the middle p⁺/n-well node, served as a Vss node of SRAM, was connected with the n-well through a metal layer, the surface potential of the n-well will also be in positive 1 V.

Figure 5-3 shows brightness contrast in the p-substrate and p⁺ region, the n-well region shows a darkness contrast. Figure 5-4 is a magnification of the SEPC image shown in Fig. 5-3. Two poly silicon gates and three p⁺/n-well junctions are visible. The left and right p⁺/n-well junctions show brightness contrast. The figure clearly shows not only the p⁺/n-well, but also the lightly-doped drain region (p^- region). This confirmed the good spatial resolution of the SPEC method. Contrast is low in the middle p⁺/n-well junction since it acts as a Vss node of the SRAM and is connected with the n-well region with positive 1 V. In experiment, doping contrast could not be observed before the electricity biasing. The doping contrast was restored when the electricity was triggered in the junction, which indicates that SEPC is affected by the surface potential of the specimen.

5.3.2 p⁺/n-well Junction Profile with Two Nano-probes Biasing

On the behalf of the nano-probe system, the p⁺/n-well junction nodes could be applied in a reverse biased condition with two nano-probes. Figure 5-5 shows the SEM image that corresponds to Fig. 5-2. An SEPC signal is clearly observed on the right-most p⁺/n-well junction when the probe tips were electrically biased with a trigger voltage of -1V on the p⁺ side and 0V on the n-well side. In contrast, no SEPC signal is observed at the other two pairs of p⁺/n-well junctions that were not probed by the nano tips in Fig. 5-2. This result is attributable to the fact that a semiconductor junction with a small energy bandgap cannot easily be examined using the standard SEPC approach. Moreover, the method that is

presented in this work provides a good spatial resolution, even for an image of a lightly-doped drain region (p^- region).

5.3.3 Digital Image Processing of SEPC Image

To further elucidate device physics, a series of data analyses of p⁺/n-well intensity profile was performed. A p⁺/n-well junction consists of three regions a p⁺ region, a depletion region and a well region. The p⁺ and n-well regions are maintained at a steady voltage because their resistivity is lower than that of with the depletion region, and most of the reversed voltage is across the depletion region. Elliott et al. found that the SEPC intensity of a sample is proportional to the potential of the silicon surface [27]. Therefore, the image intensity simply reflects the potential of the sample, to which it is proportional. To obtain more information on the physics of the device, the image processing in Fig. 5-5 was applied.

Figure 5-6 presents the intensity profile of the p⁺/n-well junction that is obtained by a series of image processing procedures. The inset in Fig. 5-6 shows a highlighted vertical red line represents the location used for intensity profile extraction. Every point in the intensity profile is an average over a point and its four adjacent points. Three regions are indicated in Fig. 5-6.

In the p⁺ region, the rapid drop in the intensity reflects the contact that makes with the tungsten plug. It is followed by a steady brightness region.with an intensity of 3.6 × 10⁴. Thereafter, the intensity decreases gradually, representing the depletion region of the p⁺/n-well junction. Finally, a steady intensity of 1.5 × 10⁴ is observed, representing the well

region. Device physics illustrate two stable voltage levels on the p⁺ and n-well sides of a biased p⁺/n-well diode, and most of the voltage drop occurs in the depletion region. Therefore, the two stable contrast regions represent the p⁺ and n-well regions, and the gradually declining contrast represents depletion region, which is consistent with device physics. The depth of the p⁺ region and depletion region were measured to be 80 nm and 100 nm, respectively, closely matching the designed depth. The pink curve in the Fig. 5-6 represents the polynomial regression fit result under the neglecting of the silicide region. Elliot et al. reported that the SEPC intensity in a biased silicon diode is proportional to the built-in voltage, which indicates that the image intensity reflects the surface potential of the specimen [27]. So the polynomial regression fit curve in the Fig. 5-6 was converted proportionally into voltage scale, in which the p⁺ region and n-well region are set in -1 V and 0 V, respectively. Figure 5-7 shows the surface potential profile of the p⁺/n-well junction after conversion. The electrical field curve could be deduced by the first derivative of the surface potential curve. The electrical junction is located on the maximum point of the minus sign of electrical field. The measurement data show the depth of electrical junction is 123 nm. The proposed method successfully used SEPC to identify the depletion region and the electrical junction. The SEPC was used as a voltage mapping tool instead of matching it with carrier concentration as in previous works.

After completing the one-dimensional (1-D) intensity profile analysis work, 2-D image processing was performed. Depending on the intensity level of the p⁺ region and the definition

in the depletion region and well region, three different colors were used: the p⁺ region, depletion region and well region were indicated in red, green, and blue, respectively. Figure 5-8 shows that the upper and lower lines of the depletion region are two parallel curves as in an actual depletion region, and the profile of the p⁺ region is as expected. The convex area on the left side of the p⁺ region is the p^- region. A 15 nm gap between the p⁺ region and the poly silicon gate is also clearly visible in Fig. 5-8. The length of the gap is a crucial data when determining the source/drain resistance of the transistor and has not been addressed until now.

5.3.4 Comparison with Silvaco Simulation Result

SIMS is an excellent tool for analyzing dopant depth profile on specific test key structure.

In the lack of adequate 2-D dopant profiling method, some semiconductor manufacturing companies use SIMS depth profile to calibrate 2-D technology computer-aided design (TCAD) process simulator. Figure 5-9 shows the 2-D voltage distribution for a biased p⁺/ n-well junction obtained using the Silvaco TCAD process simulator, which calibrated by SIMS depth profile. The accuracy of the SEPC method has been compared against the Silvaco TCAD process simulator, which calibrated by SIMS depth profile with the assumption of 100% activation ratio. Table 5-1 summarizes the measurements of the SEPC method and Silvaco TCAD process simulator. The results of the simulation show that the depletion width, electrical junction depth and gap length between p⁺ region and poly silicon gate are 100nm, 138 nm and 10 nm, respectively. The table indicates that the TCAD simulation shows a strong

p type (p⁺ and p^-) dopant diffusion behavior than the SEPC method. The discrepancy between the SEPC result and simulation results could be caused by the calibration flow, in which the assumption of activation ratio is 100%. These results reveal the inadequacy of the simulator calibration flow, in which characterization is based on SIMS depth profile.

5.3.5 n⁺/p-well Junction Profile with two Nano-probes Biasing

The experimental results confirm that the in-situ nano-probe system is a promising tool for inspecting p⁺/n-well and n-well/p-well junctions. Figure 5-10 is an SEPC image of an n⁺/p-well obtained in the current study. Since the two probe tips on two n⁺ contacts had a positive 1 V, the substrate was kept at 0 V to ensure that the n⁺/p-well junction was biased under a reverse condition. The SEM images show that contrast in the n⁺/p-well junction appeared when electricity was triggered. The n⁺/p-well junction without a nano-probe tip showed no SEPC signal. However the contrast and image resolution of the n⁺/p-well junction were inferior to those in the p⁺/n-well. Venables et al. reported that n⁺ region depth is abnormally deep and bulk electric filed could be the reason hindering the SEPC inspection [26].

5.4 Summary

To conclude, the nano-probe and SEPC effectively characterized the p⁺/n-well junction and confirmed that in-situ biasing is a promising method for junction profiling in an actual SRAM chip. The method could be used to maintain the junction in a stable voltage condition

in order to eliminate contrast reduction resulting from surface band bending and damaged surface layer. The results indicate that contrast depends mainly on the surface potential of the specimen.

Regarding qualitative junction profile inspection, the findings are also consistent with the above empirical studies. However, unlike previous studies that tried to link contrast with dopant concentration, this study is the first to link contrast with surface potential. A gradual decrease in contrast in the depletion region was observed in the reverse bias p⁺/n-well junction. The depth of electrical junction was identified after conversion image intensity to voltage scale. In the two-dimensional dopant profile analysis, the proposed method also showed sufficient spatial resolution to identify the p^- region. Finally, a 15 nm gap between p⁺ region and poly silicon gate was successfully identified. None of these results have been reported until now.

Although the method effectively characterized the p⁺/n-well junction, the image contrast and spatial resolution in the n⁺/p-well junction are inferior to those in p⁺/n-well junction.

Further studies of n⁺/p-well junctions are needed to obtain a complete contrast mechanism for SEPC. Before that the findings of this study can be used to develop an efficient junction profiling procedure for use in qualitative inspection. The findings are also applicable to other solid state diodes such as solar cells and light emitting diodes. Future studies may consider the use of SEPC as a routine monitoring method during the fabrication process.

Fig. 5-1 A partial cross-section of the SRAM chip schematically illustrates the SEPC inspection; three p⁺/n-well junctions, two polycrystalline Si gates, and a nano-probe tip are shown. The middle p⁺/n-well junction was electrically biased with a trigger voltage 1 V. The p-substrate was kept on the ground state. The colors of the left and right p⁺/n-well junctions and p-substrate illustrate the dopant contrast after electricity was biased.

Fig. 5-2 A partial cross-section of the SRAM chip to illustrate the SEPC inspection; three p⁺/n-well junctions and two polycrystalline Si gates are shown. A pair of nanoprobing tips was inserted on the right-most p⁺/n-well junction, in which an green color represents the SEPC signal when the probe tips were electrically biased with a trigger voltage of -1 V on the p⁺ side and 0V on the n-well side.

Fig. 5-3 The SEM image corresponds to Fig. 6-1, in which nano-probe tip applied to the middle p⁺/n-well node with positive 1 V and the p-substrate with ground. Dopant contrast is clearly observed with the p-substrate and

Fig. 5-3 The SEM image corresponds to Fig. 6-1, in which nano-probe tip applied to the middle p⁺/n-well node with positive 1 V and the p-substrate with ground. Dopant contrast is clearly observed with the p-substrate and