Chapter 1 Introduction
1.4 Overview of defect isolation by SEPC
As the dimensions of transistors are scaling, the demand for an inspection tool with good spatial resolution has increased. Moreover, the transistor number of a VLSI containsbillion of transistors, indicating that this inspection tool should be able to analyze as many transistors as possible. With the improvements of electron guns and reduction of aberrations, SEM image resolution has improved to the nm scale and with a large view field. Additionally, the
secondary electron in SEM is sensitive to the voltage distribution of the inspected surface, facilitating inspection of high-resistance defects on ICs [14-16]. The contrast phenomenon arises from the influence of surface potential, and is called SEPC, or voltage contrast (VC) [17].
The SEPC effect was first observed in 1941 by Knoll [18]. Hardy et al. characterized SEPC with a voltage precision of 50 mV in the range of -30–30 V [19]. Aton et al. and Manhant-Shetti et al. demonstrated that standard SEM can isolate continuity failure of a special IC test pattern [20, 21]. The detection limit was 2 × 1011 Ohm [21]. Sakai et al. biased the test pattern to lower the detection limit to 1 × 104 Ohm [22]. Colvin utilized SEPC to isolate gate oxide leakage [23]. The SEPC arises from surface potential after electron beam irradiation [24]. This method has a contactless capability in voltage investigations and has been adopted for IC debugging [25].
1.5 Overview of dopant profiling by SEPC
Modern microelectronic IC technology enhances the performance of transistor through scaling down of transistor [5, 6]. The distribution and concentration of dopant is the key to enhance device performance when developing nano-scale devices. With a sensitivity from 1016 to 1020 cm-3 and a spatial resolution of 10 nm, the SEPC effect in SEM has emerged as the potential method for dopant profiling [26, 27]. In addition, SEPC arise from the built-in potential across the diode, indicating this is an electrical measurement method which collects
active dopant signal only [27].
The dopant contrast in SEM was first observed in 1967 by Change and Nixon [28]. After that, researchers have been investigating the dopant contrast mechanism and each group has proposed its own proposal. Pervoaic et al. and Turan et al. proposed that surface potential determines secondary electron emission rate [29, 30]. Sealy et al. and Muzzo et al proposed that a patch field outside the specimen is a major factor in dopant contrast [31, 32]. Figure 1-11 shows the simulation result that the built in potential initiates an electrical field outside the specimen [32]. The electrical field will repel electron out the p-type node, but attract electron back to specimen in n-type node, resulting the brightness and darkness contrast in p type node and n type node, respectively. Hsiao et al. observed that the strain effects will influence dopant contrast [33]. Elliott et al. and Venables et al. reported that the SEPC profile of a p+/n-well junction shows a linear relationship with the logarithm of the SIMS depth profile and their results are shown in Figure 1-12 [26, 27]. SIMS is a dopant profiling tool by collecting the all dopant elements no matter is it an active dopant or not. Figure 1-13 shows the Elliott’s study on a biased junction [27]. Elliot found that the SEPC intensity is proportional to the biased voltage, indicating the surface potential determines the secondary electron emission rate [27].
1.6 Overview of dopant profiling techniques 1.6.1 Secondary ion mass spectrometry (SIMS)
SIMS is an analytical tool with high sensitivity and a wide dynamic detection range. The tool sputters the specimen surface using a primary ion beam and measures the elements using a mass spectrometer. The SIMS detection limit is 1012–1016 cm-3, and depends on material type [34]. With careful calibration of sputtering rate and low primary ion energy, SIMS has been used widely to characterize the depth profile of shallow junctions in CMOS devices [35].
However, SIMS is a destructive analytical method that depicts the dopant profile by sputtering the analytical target to mass spectrometer. All sputtered elements will be guided to the mass spectrometer and counted in the depth profile. Target dimensions should be larger than 50 × 50 µm, meaning that SIMS cannot be applied in the site-specific real circuit.
1.6.2 Scanning capacitance microscope (SCM)
SCM is a scanning probe microscope that uses a tiny tip to scan a specimen and record the capacitance response. Williams conducted the two-dimensional dopant profiling via SCM with a 10 nm spatial resolution [36]. A high-quality oxide should be grown in a specimen’s surface for reliable measurement, making the repeatability of SCM poor for many samples.
Figure 1-14 shows schematic to illustrate the SCM operation principle [36].
1.6.3 Kelvin force probe microscope (KFPM)
KFPM combines AFM and SCM to map the electrostatic voltage difference between the tip and specimen surfaces [37]. The electrostatic force between the tip and specimen under a constant range, Z, is given by
dZ
F =1/2dC V2……….(1)
where C is coupling capacitance and V is electrostatic voltage between the tip and specimen [37]. Surface potential is determined as measured electrical force, coupling capacitance, and tip potential. Figure 1-15 shows the KFPM system [37].
1.6.4 Electron holography
Electron holography is also a surface potential mapping method that uses interference of an off-axis electron beam in transmission electron microscope (TEM) [38]. With improved spherical aberration and a field emission gun, Griyelyuk et al. reported a 2D diode potential mapping with a spatial resolution of 6 nm and voltage sensitivity of 0.17 V [39]. However, an accurate potential map requires a sample with uniform thickness, such that electron holography is rarely used in IC manufacturing.
1.6.5 Chemical delineation
Chemical delineation uses acids to etch heavily doped areas selectively [40]. The silicon surface is first oxidized to silicon dioxide (SiO2) by nitric acid and then dissolved into a solution by fluride acid. The etching rate is limited by the concentration of holes in the sample surface [41]. The etching rate of n+ Si can be enhanced by band bending in solution, accumulating holes in the n+ surface. The etching rate of p+ silicon can be enhanced by anodic biasing, creating holes in the p+ surface [42]. However, this method has difficulty identifying the precise well profile due to low dopant dosages. Further, wet etching methods are
destructive, meaning that the doping area will be etched out permanently.
1.7 Motivations of study
Transistors are built with solid materials and using their semiconductor electrical properties to perform complex computations. SEM has been widely used to inspect physical and electrical transistor properties. For instance, people use the secondary electron (SE) to measure transistor dimensions, use the backscattered electron (BSE) to inspect element contrast, and use the Auger electron and X-rays for element analysis. The SE contrast, which arises from the differences in surface potential, is called SE potential contrast (SEPC) and can be used to inspect electrical transistor properties. The SEPC has been widely applied in electrical defect isolation and dopant profiling.
Even though experimental results demonstrate that SEPC is an efficient method for continuity failure isolation, failure mode of an IC is not just a continuity issue. Four node types are used in VLSI chips, polysilicon gate node, n+/p-well node, p+/n-well node, and well nodes [43]. The traditional SEPC method cannot distinguish between all node types. This study investigates the SEPC by varying primary electron energy and discusses the source of potential contrast without additional biasing. Finally, this study offers a procedure to distinguish between different nodes in a chip.
In application of dopant profiling, many studies have applied SEPC for electrically active dopant profile mapping [31, 32]. However, as the device has nano-scale dimensions, the study
of SEPC in real circuit is rarely reported. The spatial resolution, site-specific analytical capability and poor SEPC signal in small bandgap material are emerging as the top three issues in SEPC method [44, 45]. Jepson et al. observed that the SEPC spatial resolution is improved in helium ion microscopy (HeIM) [46, 47]. Kazemian et al study of using focused ion beam (FIB) on sample preparation to meet the requirements for site-specific analysis [48].
However the SEPC is significantly reduced due to the damage layer generated by FIB, as shown in Figure 1-16 [48]. Hence, this study fills the gap in the literature by enhancing dopant contrast with nano-probe assistance. In addition, author converts the SEPC image to a voltage scale and elucidates theoretical description about the device physics [49-51].
1.8 Organization of the thesis
In chapter 1, the CMOS technology revolutions and process characterization challenges are introduced. We also have brief overview of the physical and electrical properties of the pn diode. The applications of CMOS technology in the logic circuit, SRAM, and LDMOS are also addressed in chapter 1. Additionally, the overview of defect isolation and dopant profiling using SEPC, and techniques for dopant profiling are also summarized in chapter 1. In chapter 2, the experimental instruments, sample preparation methods, electrical and physical characterization techniques are presented. This chapter introduces the secondary electron in SEM, sample milling tool FIB, electrical measurement tool nano-probe system and AFM.
In chapter 3, the SEPC effect with varying primary electron beam energy is investigated.
A procedure is suggested to distinguish all node types in chip. Finally, this new procedure is applied in a real case and isolates defect successfully. Next, in chapter 4, the sample preparation methods for SEPC in dopant contrast inspection are examined. And a application of SEPC in p+/n-well junction leakage is presented. In chapter 5, this chapter investigates the use of SEPC with an in-situ nano-probe biasing to examine a silicon p+/n-well junction. The SEPC image is digitalized to elucidate the physics of diode. In Chapter 6, the mismatch mechanism in a current mirror was investigated using a SEM with in-situ nano-probe biasing.
In Chapter 7, we summarize the experimental results and give a conclusions and suggestions in future works.
Figure 1-1 Transistor counts of microprocessor (thousands) versus years. [1]
Figure 1-2 Logic technology node and transistor gate length over time. [2]
Figure 1-3 (a) Band gap diagram of p-type and n-type semiconductors. (b) Band gap diagram of a p/n junction in thermal equilibrium. [7]
Figure 1-4 (a) The space charge distribution of a linearly-graded junction.
(b) The electrical field of the junction. (c) The electrical potential of the junction. (d) The band diagram of the junction [7]
Figure 1-5 (a) The band diagram of a diode under thermal equilibrium. (b) The band diagram of a diode in forward bias condition. (c) The band diagram of a diode in reverse bias condition. [7]
Figure 1-6 The current voltage characteristics of the diode. [7].
Figure 1-7 (a) The radiation mechanism of a forward biasing diode. (b) The photon detection mechanism of reverse biasing diode. [8]
Figure 1-8 Schematic illustrats the cross-sectional structure of the CMOS technology.
Figure 1-9 (a) The circuit of a SRAM bit cell. (b) The layout pattern of a SRAM bit cell.
Figure 1-10 The cross-sectional structure of the lateral double diffused negative metal oxide semiconductors (LDNMOSs). [13]
Figure 1-11 The simulation result of electrical field above the unbiased SiC junction surface due to the built-in potential [32]
Figure 1-12 (a) SEPC image on a Si test structure. (b) SEM contrast profile.
(c) SIMS depth profile. [27]
Figure 1-13 The difference of SE intensity between p region and n region as a function of bias voltage. [27]
Figure 1-14 Schematic illustrates the SCM operation principle. [36]
Figure 1-15 Schematic illustrates the KFPM operation principle. [37]
Figure 1-16 The SEPC images prepared by different methods (a) The cleaving result. (b) The polishing result. (c) The FIB milling result. (d) SEPC intensity curve across junction. [48]
Chapter 2 Techniques
2.1 Sample preparation process 2.1.1 Planar sample preparation
The purpose of sample preparation is to make the specimen ready for physical and electrical characterization through mechanical and chemical treatment. In this work, the specimen is an IC chip with one poly layer and five metal layers. Planar sample preparation is using mechanical polish method to approach the target layer. The specimen is polished to contact layer for electrical measurement by nano-probe system or AFM. The mechanical polishing tool used in this work is Allied MultiprepTM and its picture is shown inFigure 2-1(a) [52]. Figure 2-1(b) shows diamond films with different color to indicate different abrasive effect [52]. The diamond film is changed from coarse to fine for minimizing the scratch in specimen surface.
2.1.2 Cross section sample preparation
The Allied MultiprepTM is also can be used in cross-section sample preparation after changing the polish head. Figure 2-1(c) shows the polish head for corss-section sample preparation [52]. In this work, the specimen is prepared in cross-section for dopant profile inspection.
2.1.3 Chemical delayer and Ar sputtering
The disadvantage of mechanical polish method is that it generates a damaged layer on the specimen surface, hindering the SEPC inspection. Chee et al reported that the chemical solution containing 40% NH4F can remove the oxide layer in Si surface and passivate the silicon surface [53]. Our study also confirms the BENEFIT effect of NH4F treatment in SEPC inspection [54]. For active area inspection, using HF solution is the most effective way for dielectric layer removing. In this work, the HF solution is used to remove the oxide layer above the active layer. In addition to chemical treatment, the Ar sputtering is also used to minimize the damaged layer thickness resulting from mechanical polishing. The apparatus we used in this work is Gatan Model 693.
2.2 Material analysis
2.2.1 Scanning electron microscope (SEM)
SEM was a primary electron beam to scan the specimen surface and collects the ejected electron by detector. The SEM model in this work is Hitachi S4700, which using field emission gun in primary electron beam generation. The interactions of primary electron beam with specimen generates characteristic signals like secondary electrons (SE), backscattered electrons (BSE), Auger electrons, and X-ray, and as shown in Figure 2-2 [17]. Figure 2-3 shows the distribution of emitted electrons after the bombardment of primary electron beam.
[24]. The secondary electron is the inelastic collision result between primary electron with
specimen and it is energy is smaller than 50 eV. On the contrary, backscattered electron is result from the elastic collision and its energy is close to the primary electron energy. Since the secondary electron energy is small, its escape depth is close to the surface, about 37 nm [48]. Figure 2-4 shows the escape depth of Si diode with FIB sample preparation [48]. The spatial resolution of the SEM is determined by the probe size of SEM. The specification of S4800, the upgrade model of S4700, possesses a 2 nm spatial resolution at 1 keV [56].
Since the energy of SE is less than 50 eV and majorly distributes at 4 eV, making SEM contrast with high correlation to the specimen surface potential [24]. SEPC shows lower contrast with positive potential. The traditional SEPC uses the fixed primary electron energy at 1 keV to isolate the continuity failure in IC [23]. The source of specimen surface potential
comes from surface charging after electron irradiation [24]. Figure 2-5 shows the schematic to illustrate the surface charging effect [24]. The SE yield (δ) is the division of emission electron number by injection electron number.δ > 1 results in positive charging in the surface and negative charging when δ < 1. Table 2-1 shows the δ and maximum primary electron energy
EPEm for CMOS materials [24]. The traditional SEPC condition 1 keV will result a positive charging in the specimen. In this work, we uses EPE =5 keV to make a negative charging in the specimen. The sample was polished to contact layer and irradiate by 1 keV and 5 keV electron beam, respectively. The SEPC images of contacts were recorded and a discussion is made to explain to contrast behavior. The second part of the thesis investigates SEPC with in-situ
nano-probe biasing to examine 2D dopant profile inspection. The dopant contrast is enhanced by nano-probe biasing and a series image process work is made to elucidate the physics of device.
The spatial resolution for SEPC is limited by the probe size of the inspection tool. Castell et al have suggested a 0.1 nm probe size of SEM for dopant mapping on the nanotechnology
age [6]. In this work, the spatial resolution of S-4700 is about 2 nm. Recently Helium Ion Microscopy (HeIM) is a new tool with probe size that is as small as 0.25 nm. Jepson et al have reported SEPC mechanism in HeIM is similar to SEM [46, 47]. Their further inspections observed that the SEPC spatial resolution is improved in HeIM, making HeIM an ideal candidate for nano-scale dopant mapping in the future [46, 47].
2.2.2 Focused ion beam (FIB)
The operation of FIB is similar to SEM, which uses a focus ion beam to image the specimen instead of focused electron beam used in SEM. The interaction between ion beam and specimen also generates secondary electron and could be used to form an image.
Additionally, the mass and momentum of ion is far more than electron, FIB will sputter the specimen surface and be a precision milling tool. The FIB apparatus used in this work is FEI DB235. Figure 2-6 shows the precise cross-sectioned milling capability of a FIB [56].
2.3 Electrical analysis 2.3.1 Nano-probe system
The nano-probe system is a transistor level electrical measurement tool. The nano-probe system in this work is DCG sProber, which equipped four positioners with 2 nm resolution of movement [57]. The sProber can be installed into the existing SEM and FIB for cost saving.
As the transistor dimension going into nano-scale dimension, the major challenges of nano-probe system are the how small of tip size can be made and how many tip counts can be put in a small area. Figure 2-7(a) shows the DCG nProber which with 8 nano positioners [58].
Figure 2-7(b) is a SEM image from nProber, showing the 8 nano tips probe in the metal 1 layer of SRAM [58]. The tip radius is smaller than 50 nm [57]. The DCG’s system also has anti-contamination function for offering a low resistance measurement [57].
The major application of a nano-probe system is to measure the electrical characteristic of a transistor. Because the transistors are covered by metal layers and passivation layer, the sample was polished to contact layer for electrical measurement. In this work, the nano tips probe on the contact to measure the Id-Vg curve of the LDMOS. In addition, nano-probe was used to bias the n-well and p-well in a reverse bias condition, enhancing the SEPC effect in SEM. The missing dopant contrast is restored after the bias is triggered on the diode nodes, offering a new application of nano-probe system.
With the feasibility of operation, several new applications have been developed. Stallcup
proposed bitcell pulsing measurement method to isolate the defective transistor of the SRAM [58]. Other applications include using electron beam induced current (EBIC) to characterize the carrier life time and electron beam absorption current to isolate the continuity failure of backend metal layers [57]. However, the electron beam irradiation may cause transistor degradation and the primary electron beam energy should be as low as possible.
2.3.2 Conductive atomic force microscope (C-AFM)
AFM uses a tiny tip to scan the specimen surface and record the atomic force interaction between tip and specimen [59, 60], including electrostatic force, van der waals force, and magnetic force…[59, 60]. Since the AFM has the atomic scale resolution, the AFM is widely adopted to measure the electrical properties, magnetic properties, and topology information of the specimen. The operation modes of AFM have non-contact mode, contact mode, and tapping mode. Figure 2-8 shows the schematic to illustrate the operation principle of a C-AFM [61].
The model of AFM in this work is Veeco Innova. The Innova is a contact mode AFM
which using a metal tip to measure the conductivity of specimen. The measuring current ranges from 2 pA to 1 µA. In this work, C-AFM was used to isolate the leakage p+/n-well
junction. The current map of C-AFM result indicates the leakage p+/n-well junction appeared in every alternative row. The misalignment of the p-well mask layer is identified as the root cause of leakage.
With high sensitivity in electrical measurement, C-AFM can be used to isolate high resistance issues and small leakage issues in CMOS technology. A four tips C-AFM system was also developed to measure the transistor’s electrical characteristic. The benefit of transistor measurement by C-AFM is no damage of transistor due to the electron beam irradiation. However, without the assistance of SEM, the transistors’ location is located by the
With high sensitivity in electrical measurement, C-AFM can be used to isolate high resistance issues and small leakage issues in CMOS technology. A four tips C-AFM system was also developed to measure the transistor’s electrical characteristic. The benefit of transistor measurement by C-AFM is no damage of transistor due to the electron beam irradiation. However, without the assistance of SEM, the transistors’ location is located by the