Chapter 7 Summaries and Future Works
7.2 Future works
Although we have taken a thorough investigation of SEPC effect in contacts with varying EPE, the contrast of contacts is characterized qualitatively only. A suggested future work is the developing of quantization process in contrast, which may be useful in identification of low leakage and high resistance defects.
According to the finding in chapter 6, the p+/n-well junction has been effectively characterized in the proposed method. However, the image contrast and spatial resolution in the n+/p-well junction are inferior to those in p+/n-well junction. In future studies, however, the emphasis should be placed on attempting to studies of n+/p-well junctions for obtaining a complete contrast mechanism for SEPC. Finally, according to the future trends in transistor scaling, one other future work is to apply the proposed in-situ biasing in HeIM, in which a probe size as small as 0.25 nm can be used, realizing HeIM an ideal candidate for nano-scale dopant mapping in the future.
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Curriculum Vitae
姓 名: 李正漢 Jeng-Han Lee
性 別: 男
出生日期: 1972 年 01 月 29 日
出 生 地: 金門縣
地 址 : 新竹市三民路 85 號 21F 之 3
學 歷 : 國立金門高中 1987 年 09 月~1990 年 06 月
國立清華大學材料科學工程學系 1990 年 09 月~1994 年 06 月
國立清華大學材料工程研究所碩士班 1994 年 09 月~1996 年 06 月
國立交通大學光電工程研究所博士班 2006 年 09 月~2011 年 11 月
論文題目: 二次電子電壓對比應用於摻雜分佈與缺陷定位之研究
Publication List
A. International Letter:
1. P. T. Liu and J. H. Lee, "Inspection of the Current-Mirror Mismatch by Secondary Electron Potential Contrast With In Situ Nanoprobe Biasing," IEEE Electron Device Letters, vol. 32, pp. 1418-1420, 2011.
2. P. T. Liu and J. H. Lee, "Profiling p+/n-well junction by nanoprobing and secondary electron potential contrast," IEEE Electron Device Letters, vol. 32, pp.
868-870, 2011.
3. P. T. Liu, J. H. Lee, Y. S. Huan, and D. Su, "Application of secondary electron potential contrast on junction leakage isolation," Applied Physics Letters, vol. 95, pp. 122105-3, 2009.
B. International Conference:
1. C. C. Ho, J. H. Lee, “Electrical diagnosis and failure analysis on tree structure circuit” Proceedings of 11th IPFA conference, pp. 197, 2004.
2. Y. S. Chen, J. H. Lee, “ Defect isolation and characterization in contacts by primary voltage adjustment” Proceedings of 29th ISTFA conference, pp. 317, 2003.
3. C. W. Wu, Jeng-Han Lee, “Advanced process defect isolation by dynamic bias condition and MCT camera” Proceedings of 29th ISTFA conference, pp. 256, 2003.
4. C.Y. Lin, J. H. Lee, “Enhanced SEM doping contrast on active area” Proceedings
of 29th ISTFA conference, pp. 87, 2003.
5. J. H. Lee, S. C. Lee, and P. X. Kuo, “Defect isolation and characterization in contacts by primary current and voltage adjustment” Proceedings of 27th ISTFA conference, pp. 381, 2001.
C. International Journal:
1. J. H. Lee, P. T. Liu, “Surface Potential Mapping of p+/n-well Junction by Secondary Electron Potential Contrast with in-situ Nano-probe Biasing”, submitted to Microelectronic Engineering, 2011.
2. J. H. Lee, Y. S. Huang, and D. H. Su, "Wafer-level failure analysis process flow,"
Electronic Device Failure Analysis, vol. 12, pp. 4-11, 2010.
D. Book Chapter:
1. J. H. Lee, Y. S. Huang, D. Su, “Wafer level failure analysis process flow”, Microelectronics Failure Analysis: Desk Reference Fifth Edition, pp.39, 2004.
E. US Patent:
1. Patent Title: Micro probing tip made by micro machine method
Inventor(s): Liu; Mingo; Lee; Jeng-Han Patent number: US 6797528
2. Patent Title: Primary ion or electron current adjustment to enhance voltage contrast,
Inventor(s): Lee; Jeng-Han; Lee; Su-Chen Patent number: US 6573736
3. Patent Title: Poly gate silicide inspection by back side etching
Inventor(s): Chen;Jung-Chin; Lee;Cheng-Han Patent number: US 6905890
4. Patent Title: Top view TEM sample preparation method for active region crystal defect
Inventor(s): Lee; Jeng-Hang Patent number: US 5935870
5. Patent Title: New SRAM layout to relax mechanical stress in STI process
Inventor(s): Wuu; Shou-Gwo; Lee; Jin-Yuan; Yaung; Dun-Nian; Lee; Jeng-Han Patent number: US 6117722
3. 專利名稱: 觀察金屬矽化物之方法 發明人: 陳榮欽; 李正漢
專利證號: TW 127299
4. 專利名稱: 上視型穿透視電子顯微鏡樣品的製備方法 發明人: 李正漢
專利證號: TW 147596
5. 專利名稱: 在記憶體電路中降低機械應力之電路佈局 發明人: 伍壽國; 李進源; 楊敦年; 李正漢
專利證號: TW 117504