General Background

1.1-1 Double Patterning Technique

The well-known Moore’s Law describes that the number of transistors on an integrated circuit (IC) chip will double every 18 months [1-2]. Since the advent of IC manufacturing, this law has been in force for decades. In order to keep up with the Moore’s Law, shrinkage in device dimensions is indispensable, which also promotes device density, operation speed, and chip functionality. In other words, for better performance and cheaper manufacturing cost, the continuous scaling of the devices is evitable. To keep pace with the law, it requires innovation to overcome several fundamental physical barriers lying ahead, and first of all is to extend the photolithography limit. According to the Rayleigh’s criterion, the resolution, R, of a photolithography technique can be expressed as follows [3]:

NA

R=k₁λ (1-1), where k1 is a system constant, λ is the wavelength of incident light, and NA is the numerical aperture of the lithography system. Based on such criterion, we could adjust the three factors of the criterion so as to boost the resolution of a lithography system [4-6]. Recently, it was reported that the double exposure (DE) technique [7], and double patterning (DP) technique [8-10] were being considered as the promising candidates to extend lithography processing beyond the 45 nm node at k1 factors below 0.30. DP is a process that splits one patterning step into two to relax the imaging fidelity requirements for small technology nodes. The most common form of DP typically decomposes a target layout pattern into two separate photomasks employing two exposure steps and subsequent etching steps. Consequently, the dimensions of the final target patterns can easily break the resolution limit with single exposure. Usually I-line stepper is not capable of sub-100 nm pattern generation owing to its long exposure wavelength of 365 nm. In this work, we develop a DP technique with conventional I-line stepper to generate sub-100 nm photoresist (PR) patterns with the goal to fabricate nano-scale

MOSFETs. Although this technique consists of two times the lithographic and subsequent etching steps, we show that the DP method could reliably generate line patterns with dimension down below 100 nm.

1.1-2 Junctionless Technique

For the sake of keeping pace with the Moore’s Law, continuously downscaling the dimension of the semiconductor devices is indispensable to maintain device functionality and make manufacturing cost cheaper. However, the traditional planar bulk MOSFET structure used in the past decades inherently consists of two PN junctions, the source/drain-to-channel junctions, and the extremely high doping concentration gradient of S/D region causes the fluctuation of diffusing impurities especially within a range of few nanometers for the nano-scale devices [11]. To precisely control the doping prolife of S/D region, it needs an excessively tight and efficient thermal process for the dopant activation, which imposes more challenges on the device fabrication with the continuous shrinkage of device dimension.

To address the aforementioned challenge of controlling the doping profile, a novel device named “junctionless (JL) field-effect transistor” has been revived recently [12-14], while the same idea has been revealed in an old patent filed by Lilienfeld in 1926 [15]. In a JL transistor, the same doping polarity and concentration are used throughout the entire device from the source, channel to drain. Furthermore, the operation of a JL transistor is different from that of an accumulation-mode device, and is inherently a gated resistor in the on-state. In particular, a JL transistor is turned off through full depletion of carriers in the channel by the gate in the off-state. Besides, the much higher doping concentration in the channel, larger than 10¹⁹ cm^-3, is the unique feature of JL transistor, and is different from an accumulation-mode transistor. Due to the inherently homogeneous doping concentration across S/D and channel in the JL transistor, no conventional p-n junctions are present in it. Therefore, the JL technique can relieve the constraints related to the formation of the ultra-shallow or ultra-abrupt junction encountered in the conventional inversion-mode (IM) transistor, thus the fabrication process can be greatly simplified and the manufacturing cost can be cheaper as well.

1.1-3 Asymmetric S/D Devices

With the dimensional scaling of the MOSFETs, it accompanies a lot of challenges including the increasingly rising off-state leakage current and the short channel effects (SCE), such as the threshold voltage (Vth) roll-off, the drain induced barrier lowering (DIBL), and bulk punch-through. As for the IC industry, which has traditionally been driven by the Moore’s Law, it has brought about catastrophic power consumption, and thus the emergent demand for lower power supply is without any description. But it also requires a coexisting reduction in the threshold voltage to sustain the device performance leveraging the Moore’s Law. Nevertheless, a concomitant increase in off-state leakage is inevitable due to the restriction of non-scalable subthreshold swing (SS). For the sake of leakage current reduction, low power consumption and good SCE immunity, optimization of the source and drain junctions separately would be an effective scheme.

The asymmetric MOSFET with asymmetric lightly-doped drain (LDD) architecture [16-17] was fabricated by using additional implantation mask, followed by formation of selective oxide deposition. However, the latent misalignment would obstruct the device scaling. Fortunately, the self-aligned asymmetric structure [18] was proposed to settle the aforementioned issue. But, unfortunately, the inevitable use of phosphoric acid would likely be another issue resulted from the gate oxide damage caused by isotropic etching of phosphoric acid. The implantation scheme is an approach to achieve an asymmetric architecture as well. As described in [19], the implementation of tilt-angle implantation facilitated the fabrication of asymmetric architecture.

Nonetheless, the shielding of denser gate electrodes would increase more challenges in the adoption of tilt-angle implantation with downscaling. On the other hand, the halo doping scheme employed in standard CMOS process certainly can be adopted to accomplish the asymmetric structure in terms of boosting the device performance as reported in [20-22]. The adoption of source-junction-only halo doping scheme can not only reduce the capacitance of n⁺p junction at the drain junction but also the electrical field of drain side. Therefore the issue of leakage current can effectively be relieved, and further the power consumption can be reduced.

With the ever-increasing concerns about the forthcoming exhaust of petroleum in the near future and the unavoidable power consumption by the IC appliances, the green technology is highly demanded for reducing the supply voltage of CMOS logic devices.

The most fundamental limitation that controls the turn-on efficiency of a transistor stems from its inherent properties related to thermodynamic carrier distribution. The

basic drift-diffusion theory gives the physical limitation on the subthreshold swing (SS) at 60 mV/dec at room temperature [23]. The concept of tunneling field-effect transistor (TFET) was proposed by Sanjay Banerjee et al. in 1987 [24] and called “surface tunneling transistor” as well in those days [24-26]. The TFET is inherently a gated p-i-n diode and certainly can be categorized as an asymmetric S/D device as depicted in Fig.

1.1, using band-to-band tunneling (BTBT) as carrier transport mechanism. As a result, TFETs do not undergo the same physical limitation as MOSFETs, and are a promising candidate for achieving sub-60 mV/dec of SS.

1.1-4 Flicker Noise Characteristics

In an electronic circuit, currents and voltages are randomly perturbed from their given values because of inextricable interference of noise. Considering the random nature of noise, it can’t be excluded thoroughly and further restricts the accuracy of measured results eventually [27-28]. Hence, in view of both science and engineering, noise is a basic problem, essential to comprehend and consider for the sake of alleviating its effects and increasing the precision of desired signals. There are many kinds of noise sources such as thermal noise, shot noise, generation-recombination (g-r) noise, random-telegraph-signal (RTS) noise, and flicker (1/f) noise [29-35]. Because the transistor dimensions have been continuously downscaled, CMOS technology has been developed for the RF and analog applications which were governed by bipolar transistors in the past [36-40]. For low-noise RF/analog applications, low 1/f noise in MOSFETs is an important requirement. Therefore, accurate MOSFET noise models are highly correlated with circuit designers as well as semiconductor manufacturers that are required to pay attention to reducing the 1/f noise in transistors.

The flicker noise in MOSFETs has been extensively studied for more than two decades [41-47]. The flicker noise, called 1/f noise as well, is the common name for the fluctuations with its power spectral density proportional to 1/f^γ, with γ close to 1, usually in the range of 0.7 to 1.3. In the past, there were two major theories to explain the physical origins of flicker noise in MOSFETs. One is the number fluctuation theory based on McWhorter’s charge trapping model [43]. The other is the bulk mobility fluctuation theory based on Hooge’s empirical relation [48].

In the carrier number fluctuation theory, the random trapping and detrapping processes of charges occurred in the oxide traps near the interface between Si channel

and SiO₂ are the culprit of flicker noise [41-42], [49-50] which was originally presented by McWhorter in 1957 [43]. The charge fluctuation influences fluctuation of the surface potential, and further the channel carrier density is modulated. The conventional number fluctuation theory predicts that the 1/f noise power in the linear region is given by

attenuation coefficient of electron wave function in the oxide and the value is typically taken to be 10⁸ cm^-1 for the Si-SiO2 system [51]; W and L are channel width and length, respectively.

On the other hand, the mobility fluctuation theory considers 1/f noise as a result of fluctuation in bulk mobility, and moreover, the spectral density in a homogeneous material based on Hooge’s empirical relation can be given by

where S_Id is the spectral density of the noise in the current; I_d is the drain current; f is the frequency; N is the number of channel carriers per unit area; α_H is the Hooge’s parameter with a value of around 2 × 10^-3 [46]; W and L are channel width and length, respectively.

Later a unified flicker noise model which was proposed by K. K. Hung [52]

incorporated both the carrier number fluctuation theory and the mobility fluctuation mechanism to explain the origin of low-frequency noise in a correlated manner. The total drain current noise power can be expressed as

2 2 coefficient and typically equals to 10⁸ cm^-1 [51]; The sign of the mobility term can be determined by fitting the expression with the measured data. For the majority of samples, the sign has to be chosen as positive. This equation is the basic expression of the unified flicker noise model. Furthermore, we can yield the input referred noise power by virtue of dividing S_Id by the square of the transconductance, and the formula

can be given by

In the past, wireless communication industry was regarded as an important part of the defense industry due to the importance of instantaneous transmission, and its mysterious muffler was gradually taken off until Cold War came to the end. People were looking forward to breaking the space constraint by virtue of wireless communication, and therefore the private enterprise found their motivation in the development of wireless communication industry nonstop. Based on the continuous development of the integrated circuit technology and the desperate demand for the people's livelihood application, it makes possible to bring out the cheap wireless communication products.

However, human beings really manifest their hungers for larger capacity of data transmission after both the convenience and timeliness of the wireless transmission are met. In the case of no longer extra bandwidth being squeezed out through both the network protocol and the developments of systematic architecture, it is the fundamental solution to obtain a large number of bandwidth by increasing the communication frequency. While using the wireless communication technology for facilitating some innovative applications such as distant and timely medical care [53], immediate disaster warning, logistics management to create better living is another important target worthy of development. Therefore, how to attain low power operation and energy-saving goals is the common objective of relative research topic. Nonetheless, the core value of wireless communication development is the high-frequency technology regardless of oncoming developments of both wireless communication technology and application.

There are various high-frequency devices including heterojunction bipolar transistor (HBT) such as AlGaAs/GaAs HBT, InGaP/GaAs HBT and InP HBT of III-V compound semiconductors [54], or silicon based devices such as SiGe HBT and CMOS [55]. For the past decades, transistors have been widely used and continuously developed because the raw material of silicon is easily obtained and the correlated fabrication process is well mature. Moreover, IC manufacturing vendors have made great efforts to scale down the device’s gate length for achieving higher operation frequency of the circuits and further encroaching in the field of high-frequency

applications in recent years. There are various RF transmission chips constructed by transistors including voltage-controlled oscillator (VCO) [56], low-noise amplifier (LNA) [57], filter, mixer, and phase-locked loop (PLL) [58]. On the other hand, the RF performance of thin-film transistors (TFTs) is expected to improve significantly by properly shrinking the dimensions of devices, and further it is demonstrated that the polycrystalline silicon TFT technology is feasible for low-cost RF IC applications such as RF identification (RFID) and RF modules integrated on display panel [59-60].