Chapter 1 Introduction
1.3 Thesis Organization
Total seven chapters are contained in this dissertation.
In Chapter 1, the related backgrounds and motivations of this dissertation are described.
In Chapter 2, we have developed a simple method adopting double-patterning (DP) technique to extend the I-line stepper limit to define nano-scale structures. Through in-line and cross-sectional scanning electron microscopy analyses of the generated
patterns, we confirmed the feasibility of the DP technique for the fabrication of nano-scale devices. Resolution capability of this technique has been confirmed to be at least 100 nm, which is much superior to the resolution limit of conventional I-line lithography. Moreover, an unexpected obstacle, the etching issue of second gate pattern, occurred in the DP process is addressed as well.
In Chapter 3, we have developed a modified DP technique with an I-line stepper and also compared several lithographic techniques implemented as promising candidates for the purpose of patterning nano-scale structures in the university-based laboratories. By virtue of in-line and cross-sectional scanning electron microscopy analyses of the generated patterns, we confirmed the feasibility of the ameliorative DP technique for generating sub-30 nm line patterns, and furthermore some features of these lithographic techniques were discussed in terms of throughput, line edge roughness (LER), critical dimension uniformity (CDU), minimum line width, etc.
In Chapter 4, we have fabricated asymmetric devices, including asymmetric halo nMOSFETs and tunneling field-effect transistors (TFETs) after demonstrating the feasibility of DP technique in Chapter 2. In addition, several device performances of symmetric and asymmetric devices are discussed in terms of both dc characteristics and reliability tests such as hot-carrier stress and flicker noise characteristics.
In Chapter 5, we have investigated the feasibility of gate-all-around (GAA) polycrystalline silicon (poly-Si) nanowire transistors with junctionless (JL) configuration by utilizing only one heavily doped poly-Si layer to serve as source, channel, and drain regions. In situ n+-doped poly-Si material features high and uniform-doping concentration, facilitating the fabrication process and reducing the process cost. Moreover, we have also investigated the impacts of other gate stacks such as TiN gate/Al2O3 dielectric and n+ poly-Si gate/oxide-nitride-oxide (ONO) dielectric, and further the performances of fabricated devices are discussed through basic electrical analyses and memory reliability characteristics compared with undoped-channel counterpart, demonstrating that the JL scheme is a promising candidate for the emerging SoP and 3D-IC or high density memory applications. On the other hand, we have demonstrated the feasibility of poly-Si technology for RF applications by virtue of both fabricating the in situ doped-channel TFTs adopted with salicide process, and furthermore characterizing the fabricated devices, including basic electrical analyses, small-signal modeling and the related parameter extraction. The results suggest the poly-Si TFT technology is applicable to low-cost RF IC and RF modules integrated on
display panel.
In Chapter 6, we conclude with summaries of the experimental results. Suggested items for future works are also given.
References
[1] P. K. Bondyopadhyay, “Moore's law governs the silicon revolution,” Proc. IEEE, vol. 86, no. 1, pp. 78-81, Jan. 1998.
[2] C. A. Mack, “Fifty years of Moore’s law,” IEEE Trans. on Semiconductor Manufacturing, vol. 24, no. 2, pp. 202-207, May 2011.
[3] James D. Plummer, Michael D. Deal, and Peter B. Griffin, “Silicon VLSI technology: Fundamentals, Practice and Modeling,” Prentice Hall Inc., New Jersey, 2000, pp. 209-213.
[4] M. Switkes and M. Rothschild, “Immersion lithography at 157 nm,” J. Vac. Sci.
Technol. B, vol. 19, no. 6, pp. 2353-2356, 2001.
[5] M. D. Levenson, N. S. Viswanathan, and R. A. Simpson, “Improving resolution in photolithography with a phase-shifting mask,” IEEE Trans. on Electron Devices, vol. ED-29, no. 12, pp. 1828-1836, Dec. 1982.
[6] M. Drapeau, V. Wiaux, E. Hendrickx, S. Verhaegen, and T. Machida, “Double patterning design split implementation and validation for the 32nm node,” Proc.
SPIE, vol. 6521, pp. 652109-01-652109-15, Mar. 2007.
[7] S. Hsu, J. Park, D. Van Den Broeke, and J. F. Chen, “Double exposure technique for 45nm node and beyond,” Proc. SPIE, vol. 5992, pp. 59921Q-1-59921Q-16, Nov. 2005.
[8] P. Rigolli, C. Turco, U. Iessi, G. Capetti, P. Canestrari, and A. Fradilli, “Double patterning overlay budget for 45 nm technology node single and double mask approach,” J. Vac. Sci. Technol. B, vol. 25, no. 6, pp. 2461-2465, 2007.
[9] L. S. Melvin III, B. S. Ward, H. Song, S. U. Rhie, K. D. Lucas, V. Wiaux, S.
Verhaegen, and M. Maenhoudt, “Exploration of etch step interactions in the dual patterning process for process modeling,” J. Vac. Sci. Technol. B, vol. 26, no. 6, pp.
2434-2440, 2008.
[10] M. Maenhoudt, J. Versluijs, H. Struyf, J. Van Olmen, and M. Van Hove, “Double patterning scheme for sub-0.25 k1 single damascene structures at NA=0.75, λ=193nm,” Proc. SPIE, vol. 5754, pp. 1508-1518, May 2005.
[11] S. Thompson, P. Packan, T. Ghani, M. Stettler, M. Alavi, I. Post, S. Tyagi, S.
Ahmed, S. Yang, and M. Bohr, “Source/drain extension scaling for 0.1 μm and below channel length MOSFETs,” in VLSI Symp. Tech. Dig., 1998, pp. 132-133.
[12] C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, and J. P. Colinge,
“Junctionless multigate field-effect transistor,” Appl. Phys. Lett., vol. 94, no. 5, p.
053511, 2009.
[13] C. W. Lee, I. Ferain, A. Afzalian, R. Yan, N. D. Akhavan, P. Razavi, and J. P.
Colinge, “Performance estimation of junctionless multigate transistors,”
Solid-State Electronics, vol. 54, no. 2, pp. 97-103, 2010.
[14] J. P. Colinge, C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A. M. Kelleher, B. McCarthy, and R. Murphy,
“Nanowire transistors without junctions,” Nat. Nanotechnol., vol. 5, no. 3, pp.
225-229, 2010.
[15] J. E. Lilienfeld, U.S. Patent 1,745,175 (filed in 1926, issued in 1930), U.S. Patent.
1,877,140 (filed in 1928 issued in 1932), and U.S. Patent 1,900,018 (filed in 1928, issued in 1933).
[16] J. F. Chen, J. Tao, P. Fang, C. Hu, “Performance and reliability comparison between asymmetric and symmetric LDD devices and logic gates,” IEEE J.
Solid-State Circuits, vol. 34, no. 3, pp. 367-371, 1999.
[17] T. Horiuchi, T. Homma, Y. Murao, and K. Okumura, “A high performance asymmetric LDD MOSFET using selective oxide deposition technique,” in VLSI Symp. Tech. Dig., 1992, pp. 88-89.
[18] C. S. Choi, K. W. Kim, and W. Y. Choi, “A new self-aligned asymmetric structure (SAAS) for 0.1 μm MOSFET technology,” in Proc. IEEE Electron Devices Meeting, 2000, pp.60-63.
[19] T. Ghani, K. Mistry, P. Packan, M. Armstrong, and S. Thompson, “Asymmetric source/drain extension transistor structure for high performance sub-50nm gate length CMOS devices,” in VLSI Symp. Tech. Dig., 2001, pp. 17-18.
[20] W. Yeh and J. Chou, “Optimum halo structure for sub-0.1 μm CMOSFETs,” IEEE Trans. on Electron Devices, vol. 48, no. 10, pp. 2357-2362, Oct. 2001.
[21] A. Bansal, and K. Roy, “Asymmetric halo CMOSFET to reduce static power dissipation with improved performance,” IEEE Trans. on Electron Devices, vol.
52, no. 3, pp. 397-405, Mar. 2005.
[22] S. Odanaka and A. Hiroki, “Potential design and transport property of 0.1-μm MOSFET with asymmetric channel profile,” IEEE Trans. on Electron Devices, vol.
44, no. 4, pp. 595-600, Apr. 1997.
[23] S. M. Sze and K. K. Ng, Physics of Semiconductor Devices, 3rd ed. New York:
Wiley, 2007.
[24] S. Banerjee, W. Richardson, J. Coleman and A. Chatterjee, “A new three-terminal tunnel device,” IEEE Electron Device Lett., vol. EDL-8, no. 8, pp. 347-349, Aug.
1987.
[25] T. Baba, “Proposal for surface tunnel transistors,” Jpn. J. Appl. Phys., vol. 31, no.
4, pp. L455-L457, Apr. 1992.
[26] William M. Reddick and Gehan A. J. Amaratunga, “Surface tunnel transistor,”
Appl. Phys. Lett., vol. 67, no. 4, pp. 494-496, July 1995.
[27] A. Van Der Ziel, Noise in Solid State Devices and Circuits, New York: John Wiley
& Sons, 1986.
[28] C. D. Motchenbacher and J. A. Connelly, Low-noise Electronic System Design, New York: John Wiley & Sons, 1993.
[29] J. B. Johnson, “Thermal agitation of electricity in conductors,” Phys. Rev., vol. 32, pp. 97-109, 1928.
[30] H. Nyquist, “Thermal agitation of electric charge in conductors,” Phys. Rev., vol.
32, pp. 110-113, 1928.
[31] F. N. Hooge, “1/f noise sources,” IEEE Trans. on Electron Devices, vol. 41, no. 11, pp. 1926-1935, Nov. 1994.
[32] G. Bosman and R. J. J. Zijlstra, “Generation-recombination noise in p-type silicon,” Solid-State Electronics, vol. 25, no. 4, pp. 273-280, Apr. 1982.
[33] N. V. Amarasinghe, Z. Celik-Butler, and A. Keshavarz, “Extraction of oxide trap properties using temperature dependence of random telegraph signals in submicron metal-oxide-semiconductor field-effect transistors,” J. Appl. Phys., vol.
89, no. 10, pp. 5526-5532, May 2001.
[34] G. Ghibaudo and T. Boutchacha, “Electrical noise and RTS fluctuations in advanced CMOS devices,” Microelectron. Reliab., vol. 42, pp. 573-582, 2002.
[35] P. Dutta and P. M. Horn, “Low-frequency fluctuations in solids: 1/f noise,” Rev.
Mod. Phys., vol. 53, no. 3, pp. 497-516, 1981.
[36] P. H. Woerlee, M. J. Knitel, R. van Langevelde, D. B. M. Klaassen, L. F. Tiemeijer, A. J. Scholten, and A. T. A. Zegers-van Duijnhoven, “RF-CMOS performance trends,” IEEE Trans. on Electron Devices, vol. 48, no. 8, pp. 1776-1782, Aug.
2001.
[37] A. A. Abidi, “RF CMOS comes of age,” in Proc. Symp. VLSI Circuits, 2003, pp.
113-116.
[38] J. J. Liou and F. Schwierz, “RF MOSFET: recent advances, current status and
future trends,” Solid-State Electronics, vol. 47, no. 11, pp. 1881-1895, Nov. 2003.
[39] A. Mercha, W. Jeamsaksiri, J. Ramos, D. Linten, S. Jenei, P. Wambacq and S.
Decoutere, “Impact of scaling on analog/RF performance,” in Proc. IEEE Int.
Conf. Solid-State and Integrated Circuits Technology, 2005, pp. 147-152.
[40] K. Lee, I. Nam, I. Kwon, J. Gil, K. Han, S. Park and B.-I. Seo, “The impact of semiconductor technology scaling on CMOS RF and digital circuits for wireless application,” IEEE Trans. on Electron Devices, vol. 52, no. 7, pp. 1415-1422, July 2005.
[41] S. T. Hsu, “Surface state related 1/f noise in MOS transistors,” Solid-State Electronics, vol. 13, no. 11, pp. 1451-1459, 1970.
[42] H. S. Fu and C. T. Sah, “Theory and experiments on surface 1/f noise,” IEEE Trans. on Electron Devices, vol. ED-19, no. 2, pp. 273-285, 1972.
[43] A. L. McWhorter, 1/f noise and germanium surface properties, in Semiconductor Surface Physics. Philadelphia: University of Pennsylvania Press, 1957, p.207.
[44] H. Mikoshiba, M. Sakamoto and S. Thompson, “Characterization of 1/f noise in MOS transistors,” in IEDM Tech. Dig., 1982, p. 662.
[45] H. Mikoshiba, “1/f noise in n-channel silicon-gate MOS transistors,” IEEE Trans.
on Electron Devices, vol. ED-29, no. 6, pp. 965-970, 1982.
[46] F. N. Hooge, “1/f noise,” Physica, vol. 83B, pp. 14-23, 1976.
[47] K. K. Hung, P. K. Ko, C. Hu and Y. C. Cheng, “Flicker noise characteristics of advanced MOS technologies,” in IEDM Tech. Dig., 1988, p. 34.
[48] F. N. Hooge, “1/f noise is no surface effect,” Phys. Lett. A, vol. 29a, pp. 139-140, 1969.
[49] S. T. Hsu, “Low frequency noise in MOS transistors,” Solid-State Electronics, vol.
13, no. 11, pp. 1451-1459, 1970.
[50] S. T. Hsu, “Surface state related 1/f noise in MOS transistors,” Solid-State Electronics, vol. 13, no. 11, pp. 1451-1459, 1970.
[51] S. Christensson I. Lundstrom and C. Svensson, “Low frequency noise in MOS transistors-I Theory,” Solid-State Electronics, vol. 11, no. 9, pp. 797-812, 1968.
[52] K. K. Hung, P. K. Ko, C. Hu and Y. C. Cheng, “A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors,” IEEE Trans. on Electron Devices, vol. 37, no. 3, pp. 654-665, 1990.
[53] E. Jovanov, A. Milenkovic, C. Otto and P. C de Groen, “A wireless body area network of intelligent motion sensors for computer assisted physical
rehabilitation,” J. NeuroEngineering and Rehabilitation, vol. 2, no. 6, pp. 1-10, 2005.
[54] O. Esame, Y. Gurbuz, I. Tekin and A. Bozkurt, “Performance comparison of state-of-the-art heterojunction bipolar devices (HBT) based on AlGaAs/GaAs, Si/SiGe and InGaAs/InP,” Microelectronics Journal, vol. 35, no. 11, pp. 901-908, 2004.
[55] J. D. Cressler, “SiGe HBT technology: a new contender for Si-based RF and microwave circuit applications,” IEEE Trans. Microwave Theory & Tech., vol. 46, no. 5, pp. 572-589, 1998.
[56] J. Craninckx and M. S. J. Steyaert, “A 1.8-GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors,” IEEE J. Solid-State Circuits, vol. 32, no.
5, pp. 736-744, 1997.
[57] T. K. Nguyen, C. H. Kim, G. J. Ihm, M. S. Yang and S. G. Lee, “CMOS low-noise amplifier design optimization techniques,” IEEE Trans. Microwave Theory &
Tech., vol. 52, no. 5, pp. 1433-1442, 2004.
[58] I. A. Young, J. K. Greason and K. L. Wong, “A PLL clock generator with 5 to 110 MHz of lock range for microprocessors,” IEEE J. Solid-State Circuits, vol. 27, no.
11, pp. 1599-1607, 1992.
[59] J. L. Botrel, O. Savry, O. Rozeau, F. Templier and J. Jomaah, “Polysilicon high frequency devices for large area electronics: characterization, simulation and modeling,” Thin Solid Films, vol. 515, no. 19, pp. 7422-7427, 2007.
[60] Y.-J. E. Chen, Y.-J. Lee and Y.-H. Yu, “Investigation of polysilicon thin-film transistor technology for RF application,” IEEE Trans. Microwave Theory & Tech., vol. 58, no. 12, pp. 3444-3451, 2010.
[61] P. Packan, S. Akbar, M. Armstrong, D. Bergstrom, M. Brazier, H. Deshpande, K.
Dev, G. Ding, T. Ghani, O. Golonzka, W. Han, J. He, R. Heussner, R. James, J.
Jopling, C. Kenyon, S-H. Lee, M. Liu, S. Lodha, B. Mattis, A. Murthy, L. Neiberg, J. Neirynck, S. Pae, C. Parker, L. Pipes, J. Sebastian, J. Seiple, B. Sell, A. Sharma, S. Sivakumar, B. Song, A. St. Amour, K. Tone, T. Troeger, C. Weber, K. Zhang, Y.
Luo and S. Natarajan, “High performance 32 nm logic technology featuring 2nd generation high-k + metal gate transistors,” in IEDM Tech. Dig., 2009, p. 659.
[62] K. H. Chen, C. Y. Chien, P. W. Li and O. Adams, “Precise Ge quantum dot placement for quantum tunneling devices,” IEEE Trans. Nanotechnology, vol. 21, no. 5, p. 055302, 2010.
[63] R. F. Pease and S. Y. Chou, “Lithography and other patterning techniques for future electronics,” Proceedings of the IEEE, vol. 96, no. 2, pp. 248-270, 2008.
[64] M. Shibata, A. Horiba, Y. Nagaoka, H. Kawata, M. Yasuda and Y. Hirai,
“Process-simulation system for UV-nanoimprint lithography,” J. Vac. Sci. Technol.
B, vol. 28, pp. C6M108-C6M113, 2010.
[65] H. Wang, M. Chan, S. Jagar, Y. Wang and P. K. Ko, “Submicron super TFTs for 3-D VLSI applications,” IEEE Electron Device Lett., vol. 21, no. 9, pp. 439-441, Sep. 2000.
[66] E. K. Lai, H. T. Lue, Y. H. Hsiao, J. Y. Hsieh, C. P. Lu, S. Y. Wang, L. W. Yang, T.
Yang, K. C. Chen, J. Gong, K. Y. Hsieh, R. Liu and C. Y. Lu, “A multilayer stackable thin-film transistor (TFT) NAND-type Flash memory,” in IEDM Tech.
Dig., 2006, p. 41.
[67] X. Duan, C. Niu, V. Sahi, J. Chen, J. W. Parce, S. Empedocles and J. L. Goldma,
“High-performance thin-film transistors using semiconductor nanowires and nanoribbons,” Nature, vol. 425, no. 6955, pp. 274-278, Sep. 2003.
[68] H. C. Lin and C. J. Su, “High-performance poly-Si nanowire NMOS transistors,”
IEEE Trans. Nanotechnol., vol. 6, no. 2, pp. 206-212, Mar. 2007.
[69] M. Im, J. W. Han, H. Lee, L. E. Yu, S. Kim, C. H. Kim, S. C. Jeon, K. H. Kim, G.
S. Lee, J. S. Oh, Y. C. Park, H. M. Lee and Y. K. Choi, “Multiple-gate CMOS thin-film transistor with polysilicon nanowire,” IEEE Electron Device Lett., vol.
29, no. 1, pp. 102-105, Jan. 2008.
[70] C. J. Su, T. I. Tsai, Y. L. Liou, Z. M. Lin, H. C. Lin and T. S. Chao,
“Gate-all-around junctionless transistors with heavily doped polysilicon nanowire channels,” IEEE Electron Device Lett., vol. 32, no. 4, pp. 521-523, Apr. 2011.
[71] S. Zhang, C. Zhu, J. K. O. Sin, J. N. Li and P. K. T. Mok, “Ultra-thin elevated channel poly-Si TFT technology for fully-integrated AMLCD system on glass,”
IEEE Trans. on Electron Devices, vol. 47, no. 3, pp. 569-575, Mar. 2000.
TFET
Gate
p
+n
+source drain
Tunneling junction
TFET
Gate
p
+n
+source drain
Tunneling junction
Fig. 1-1 Schematic diagram of a TFET.
Chapter 2
A Simple Method for Sub-100 nm Pattern Generation with I-line Double Patterning Technique
2.1 Introduction
Since the advent of integrated circuit (IC), lithography has been playing a critical role in semiconductor manufacturing for the sake of achieving shrinkage in device dimensions and keeping up with the Moore’s Law. Figure 2-1 illustrates the historical trends of transistor cost and feature size for CMOS during the past three decades [1]. In fact, the successful evolution of IC technology very closely counts upon the advancement of lithography instruments and associated processes. 32 nm technology node mass production of nano-scale ICs employs the immersion lithography tools with the ArF-193nm excimer laser to generate the nano-scale patterns [2]. Nevertheless, the extremely high cost on the skyrocketing lithography tool and related process is not usually affordable in the laboratories of universities. On the other hand, electron-beam (e-beam) lithography [3] is therefore far more popular in the universities for generating sub-100 nm patterns, although the throughput is dramatically limited as compared with photolithography methods, and thus its proliferation in mass manufacturing is prohibited.
I-line steppers have been employed for a long time for both manufacturing and research purposes, and the associated lithographic process is very mature and reliable.
However, for conventional I-line process, the line width of generated photoresist (PR) pattern is typically 0.3 μm or wider. Although nano-scale dimensions can be achieved by combining with the PR ashing scheme [4-5], a highly stable asher is necessary to ensure good reproducibility and uniformity of critical dimension (CD) of the printed patterns. Besides, rounding of the top PR can be another concern for subsequent etching step [5]. Recently, it was reported that the double exposure (DE) technique [6], and double-patterning (DP) technique [7-12] were being considered as promising candidates to extend lithography processing beyond the 45 nm node at k1 factors below 0.30.
Furthermore, DP technique has been considered as a viable approach for sub-32-nm
nodes by integrating with the immersion ArF-193-nm process [13].
In this chapter, we propose a simple method which combines both I-line lithographic process and DP technique to address the aforementioned issues. As compared with the e-beam direct writing method, I-line process surpasses in throughput but is much worse in resolution capability which can be ascribed to the optical diffraction phenomenon. On the other hand, DP technique which typically requires twice lithographic and/or etch steps has been proposed to increase the density of devices [7-8] and has also been demonstrated with the capability of breaking the resolution limit of an optical system [9-10]. Even with the I-line process, generated structures with nano-scale dimensions can be expected if the DP technique is incorporated. Hence, we exploit such feasibility by successfully fabricating and characterizing both nano-scale n-channel metal-oxide-semiconductor field-effect transistors (n-MOSFETs) and p-MOSFETs. Besides, an issue encountered in polycrystalline silicon (poly-Si) gate electrode etch step of the proposed method is presented and discussed as well.
2.2 Development of Double Patterning with I-line Stepper
To implement the above-mentioned DP technique, it is necessary to ensure the feasibility of DP scheme. For all lithographic steps carried out in this work, we used an I-line stepper (Canon FPA-3000i5+) to generate PR patterns. Fundamental process steps of the proposed scheme for forming the test patterns are shown in Fig. 2-2. The poly-Si film was deposited on a six-inch Si substrate capped with a thermal oxide layer (100 nm) as shown in Fig. 2-2 (a), followed by the first lithographic step [Fig. 2-2 (b)].
Afterwards, the regions of exposed poly-Si layer were etched with a reactive plasma step, as shown in Fig. 2-2 (c). In Fig. 2-2 (d), the second lithographic step was employed to generate PR patterns which covered portions of the poly-Si layer remained on the surface of the substrate, followed by a reactive plasma etching step to complete the final poly-Si structure [Fig. 2-2 (e)]. With suitable design and process control, the dimension of final poly-Si line patterns [Fig. 2-2 (f)] could be scaled well below 100 nm.
This procedure employed two masks denoted as G1 and G2 to define the gate electrode, as shown in Fig. 2-3. As can be seen in Fig. 2-3, the most critical portion in the design is the overlapped region of the two gate patterns in the active area which determines the channel length (Lovp) of the fabricated device. In-line and cross-sectional scanning electron microscopy (SEM) techniques were used to characterize and verify the
resultant PR and etched poly-Si structures formed by DP technique.
2.3 Devices Fabrication
The above DP process has also been implemented in practical n-MOSFET and p-MOSFET fabrication for forming 120 nm gate patterns, and the fabricated n-MOSFETs were performed on 6-inch p-type (100) bare Si wafers (n-type bare Si wafers for p-MOSFETs). Figure 2-4 illustrates the major process steps in the fabrication of MOSFETs with the DP technique. First, local oxidation of Si (LOCOS) scheme was used for device isolation. P-type well for n-MOSFETs (n-type well for p-MOSFETs) was formed by the implantation of BF2+
with energy of 70 keV and dose of 1×1013 cm-2 (P31+
with energy of 120 keV and dose of 7.5×1012 cm-2), followed by a drive-in anneal step at 1100 oC. Channel stop implantation was performed by implanting BF2+ (120 keV, 4×1013 cm-2) for n-MOSFETs and As+ (120 keV, 3×1012 cm-2) for p-MOSFETs.
Anti-punchthrough (APT) and threshold voltage (Vth) adjustment implantations of n-MOSFETs were performed individually by implanting B+ (70 keV, 2×1012 cm-2) and BF2+
(90 keV, 1×1013 cm-2), and those for p-MOSFETs were P31+
(120 keV, 7.5×1012 cm-2) and As+ (120 keV, 3×1012 cm-2), respectively. Thermal gate oxide of about 3 nm was grown in an N2O ambient of a vertical furnace, followed by the deposition of a 150 nm-thick in situ phosphorous-doped poly-Si layer (undoped poly-Si layers for p-MOSFETs) to serve as the gate electrode, as shown in Fig. 2-4 (a). Gate implant was implemented only for p-channel devices by implanting BF2+
(15 keV, 5×1015 cm-2), followed by gate dopant activation at 900 °C for 30 seconds. Afterwards, DP technique was executed to pattern the poly-Si gate. The two lithographic processes of DP scheme using G1 and G2 masks were aligned with the preexisting zero-layer alignment mark formed on the wafer. Mask G1 was first applied to generate PR patterns covering portions of the poly-Si, as shown in Fig. 2-4(b), followed by a reactive ion etch (RIE) step done by a Lam-TCP9400 to remove the uncovered poly- Si. The second lithographic step with mask G2 was then employed to generate PR patterns which covered portions of the poly-Si layer remaining on the surface of the substrate [Fig. 2-4 (c)], followed by an RIE step to complete the final poly-Si structure. After the gate patterning [Fig. 2-4 (d)], the source/drain (S/D) extensions were formed by implanting As+ (10 keV, 1×1015cm-2) for n-MOSFETs and BF2+ (10 keV, 5×1014 cm-2) for p-MOSFETs. In addition, the n-MOSFET halo implantations were executed by
implanting BF2+ (50 keV, 2.5×1012 cm-2, tilt angle =45°) denoted as N-HALO, while p-MOSFET halo implantations were executed by implanting As+ (50 keV, 2.5×1012 cm-2, tilt angle =45°) denoted as P-HALO. Some wafers skipping the halo implantations, denoted individually as NMOS and PMOS, serve as the controls. After forming a 100 nm-thick TEOS sidewall spacer, deep S/D junctions were formed by implanting As+ (20 keV, 5×1015cm-2), and then rapid thermal anneal (RTA) was then individually carried out in a nitrogen ambient at 1000 oC for 10 seconds (n-MOSFETs) and spike-1000 oC (p-MOSFETs) to activate dopants in the gate and S/D junctions, as depicted in Fig. 2-4 (e). Finally, 680 nm-thick TiN/AlSiCu/TiN/Ti metallization was carried out in a PVD system to form the metal pads, and then the processing steps were completed with a forming gas anneal at 400 °C for 30 minutes. The overall implantation conditions used
implanting BF2+ (50 keV, 2.5×1012 cm-2, tilt angle =45°) denoted as N-HALO, while p-MOSFET halo implantations were executed by implanting As+ (50 keV, 2.5×1012 cm-2, tilt angle =45°) denoted as P-HALO. Some wafers skipping the halo implantations, denoted individually as NMOS and PMOS, serve as the controls. After forming a 100 nm-thick TEOS sidewall spacer, deep S/D junctions were formed by implanting As+ (20 keV, 5×1015cm-2), and then rapid thermal anneal (RTA) was then individually carried out in a nitrogen ambient at 1000 oC for 10 seconds (n-MOSFETs) and spike-1000 oC (p-MOSFETs) to activate dopants in the gate and S/D junctions, as depicted in Fig. 2-4 (e). Finally, 680 nm-thick TiN/AlSiCu/TiN/Ti metallization was carried out in a PVD system to form the metal pads, and then the processing steps were completed with a forming gas anneal at 400 °C for 30 minutes. The overall implantation conditions used