Summary

In this chapter, we have developed a simple method which combines both I-line lithographic process and DP technique to accomplish nano-scale pattern generation, and confirmed such feasibility by successfully fabricating and characterizing both 120 nm n-/p-MOSFETs. In comparison with the conventional single-patterning method, the DP technique displays better CD control and acceptable throughput, as have been demonstrated in our study. Besides, through both in-line and cross-sectional SEM analyses, we further manifested the present I-line DP technique is a promising candidate for the purpose of patterning sub-100 nm structures in the university-based laboratories.

Finally, the impact of halo on device performance is discussed, including short-channel effect, current drivability and Vth roll-off. We have found that the halo implantation would improve the SCEs and reduce the subthreshold leakage. However, at the same time the halo implantation increases Vth in short-channel devices and causes the severe RSCE, resulting in the degradation of driving current. In short, it is very important to optimize the halo implant for nano-scale device manufacturing.

References

[1] S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T.

Ghani, G. Glass, T. Hoffman, C.-H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Z. Ma, B.

Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, P. Nguyen, S.

Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy,

“A 90-nm logic technology featuring strained silicon,” IEEE Trans. on Electron Devices, vol. 51, no. 11, pp. 1790-1797, 2004.

[2] P. Packan, S. Akbar, M. Armstrong, D. Bergstrom, M. Brazier, H. Deshpande, K.

Dev, G. Ding, T. Ghani, O. Golonzka, W. Han, J. He, R. Heussner, R. James, J.

Jopling, C. Kenyon, S-H. Lee, M. Liu, S. Lodha, B. Mattis, A. Murthy, L. Neiberg, J. Neirynck, S. Pae, C. Parker, L. Pipes, J. Sebastian, J. Seiple, B. Sell, A. Sharma, S. Sivakumar, B. Song, A. St. Amour, K. Tone, T. Troeger, C. Weber, K. Zhang, Y.

Luo and S. Natarajan, “High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors,” in IEDM Tech. Dig., 2009, p. 659.

[3] M. Drapeau, V. Wiaux, E. Hendrickx, S. Verhaegen, and T. Machida, “Double patterning design split implementation and validation for the 32nm node,” Proc.

SPIE, vol. 6521, pp. 652109-01-652109-15, Mar. 2007.

[4] S. Hsu, J. Park, D. Van Den Broeke, and J. F. Chen, “Double exposure technique for 45nm node and beyond,” Proc. SPIE, vol. 5992, pp. 59921Q-1-59921Q-16, Nov. 2005.

[5] J. Chung, M. Jeng, J. E. Moon, A. T. Wu, T. Y. Chan, P. K. Ko, and C. Hu,

“Deep-submicrometer MOS device fabrication using a photoresist-ashing technique,” IEEE Electron Device Lett., vol. 9, no. 4, pp. 186-188, 1988.

[6] K. Asano, Y.-K. Choi, T.-J. King, and C. Hu, “Patterning sub-30-nm MOSFET gate with i-line lithography,” IEEE Trans. on Electron Devices, vol. 48, no. 5, pp.

1004-1006, 2001.

[7] J. R. Sheats and B. W. Smith, “Microlithography: Science and Technology,”

Marcel Dekker Inc., New York, 1998, p. 102.

[8] K. M. Monahan, “Enabling double patterning at the 32nm node,” in Proc. IEEE International Symposium on Semiconductor Manufacturing, 2006, pp. 126-129.

[9] P. Rigolli, C. Turco, U. Iessi, G. Capetti, P. Canestrari, and A. Fradilli, “Double patterning overlay budget for 45 nm technology node single and double mask approach,” J. Vac. Sci. Technol. B, vol. 25, no. 6, pp. 2461-2465, 2007.

[10] K. Ronse, P. Jansen, R. Gronheid, E. Hendrickx, M. Maenhoudt, V. Wiaux, A.-M.

Goethals, R. Jonckheere, and G. Vandenberghe, “Lithography options for the 32 nm half pitch node,” IEEE Trans. Circuits Syst., I: Regul. Pap., vol. 56, no. 8, pp.

1883-1890, 2009.

[11] L. S. Melvin III, B. S. Ward, H. Song, S. U. Rhie, K. D. Lucas, V. Wiaux, S.

Verhaegen, and M. Maenhoudt, “Exploration of etch step interactions in the dual patterning process for process modeling,” J. Vac. Sci. Technol. B, vol. 26, no. 6, pp.

2434-2440, 2008.

[12] M. Maenhoudt, J. Versluijs, H. Struyf, J. Van Olmen, and M. Van Hove, “Double patterning scheme for sub-0.25 k1 single damascene structures at NA=0.75, λ=193nm,” Proc. SPIE, vol. 5754, pp. 1508-1518, May 2005.

[13] V. S. Basker et al., “A 0.063 μm² FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch,” in VLSI Symp. Tech. Dig., 2010, pp. 19-20.

[14] C. Y. Chang and S. Sze, “ULSI Technology,” McGraw-Hill Inc., New York, 1996, p.362.

[15] Y. Taur and T. H. Ning, “Fundamentals of modern VLSI devices,” Cambridge Univ. Press, New York, 1998, p.142.

[16] L. D. Yau, “A simple theory to predict the threshold voltage of short-channel IGFET’s,” Solid-State Electronics, vol. 17, no. 10, pp. 1059-1063, 1974.

Table 2-1 Overall implantation conditions used in the n-MOSFET fabrication.

Conditions Ion Energy / Dose / Tilt angle / Twist angle P-well BF2+

70 keV / 1×10¹³ cm^-2 / 7° / 22°

Channel Stop BF2+

120 keV / 4×10¹³ cm^-2 / 7° / 22°

Vth BF2+

40 keV / 1×10¹³ cm^-2 / 7° / 22°

APT B⁺ 35 keV / 5×10¹² cm^-2 / 7° / 22°

Halo BF₂⁺ 50 keV / 2.5×10¹² cm^-2 / 45° / 27°

S/D extension As⁺ 10 keV / 1×10¹⁵ cm^-2 / 0° / 0°

Deep S/D As⁺ 20 keV / 5×10¹³ cm^-2 / 0° / 0°

Table 2-2 Overall implantation conditions used in the p-MOSFET fabrication.

Conditions Ion Energy / Dose / Tilt angle / Twist angle N-well P₃₁⁺ 120 keV / 7.5×10¹² cm^-2 / 7° / 22°

Channel Stop As⁺ 120 keV / 3×10¹² cm^-2 / 7° / 22°

Vth As⁺ 80 keV / 1×10¹³ cm^-2 / 7° / 22°

APT P31+

120 keV / 4×10¹² cm^-2 / 7° / 22°

Halo As⁺ 50 keV / 2.5×10¹² cm^-2 / 45° / 27°

S/D extension BF₂⁺ 10 keV / 5×10¹⁴ cm^-2 / 0° / 0°

Deep S/D BF₂⁺ 15 keV / 5×10¹³ cm^-2 / 0° / 0°

Table 2-3 Specifications of Canon FPA-3000i5+ Stepper.

Fig. 2-1 Transistor cost and scaling trend of channel length versus years for technology node [1].

Fig. 2-2 Process flow of poly-Si gate formation with double patterning technique.

Fig. 2-3 Mask layouts of the first (G1) and second (G2) gate patterns for defining the gate pattern on the active region. Gate length (Lovp) of the final gate is determined by the overlap region of the two gate patterns.

Fig. 2-4 Major process steps for fabricating n-MOSFETs with the DP method. (a) Formation of gate oxide and poly-Si on Si wafer with LOCOS isolation. (b) Generation of first PR pattern (G1), followed by the first poly-Si etching. (c) Generation of second PR pattern (G2) after removing the first PR. (d) Completion of the poly-Si gate after second poly-Si etching and subsequent PR removal. (e) Formation of S/D structure.

Fig. 2-5 Typical optical emissive signal recorded during the main etching stage of the second gate etching with the original mask design. No end point was detected.

Fig. 2-6 Cross-sectional SEM view of a MOSFET showing an etch-induced recess at the right side of the gate. Top illustration is used to help visualize the structure. The recess was formed during the G2 etching stage due to the failure of EPD.

Fig. 2-7 (a) Optical emissive signal recorded during the main etching stage of the first gate etching step with the modified mask design.

Fig. 2-7 (b) Optical emissive signal recorded during the main etching stage of the second gate etching step with the modified mask design. Successful EPD is achieved in the two etch steps.

Fig. 2-8 (a) In-line SEM views of gate patterns on active region etched with original mask designs. The etch-induced damage region can be distinguished vividly.

Fig. 2-8 (b) In-line SEM views of gate patterns on active region etched with modified mask designs. The etch recess phenomenon can be resolved with the modified mask design.

Fig. 2-9 Throughput of two lithography tools.

Fig. 2-10 Mask layout for defining the gate pattern and observed area on the active region marked with a red dashed line.

Fig. 2-11 (a) In-line SEM image of a patterned poly-Si line with nominal line width of 500 nm. The measured line width in this case is 498 nm.

Fig. 2-11 (b) In-line SEM image of a patterned poly-Si line with nominal line width of 400 nm. The measured line width in this case is 390 nm.

Fig. 2-11 (c) In-line SEM image of a patterned poly-Si line with nominal line width of 300 nm. The measured line width in this case is 294 nm.

Fig. 2-11 (d) In-line SEM image of a patterned poly-Si line with nominal line width of 200 nm. The measured line width in this case is 214 nm.

Fig. 2-12 In-line SEM images of patterned poly-Si lines located at eight different dies of a wafer with nominal line width of 100 nm.

Fig. 2-13 In-line SEM images of patterned poly-Si lines located at eight different dies of a wafer with nominal line width of 80 nm.

Fig. 2-14 In-line SEM images of patterned poly-Si lines randomly located on a wafer with nominally shortest line width of 50 nm.

Fig. 2-15 Measured poly-Si gate length (L_poly) as a function of nominal gate length (L_ovp).

Fig. 2-16 Cumulative plots of poly-Si gates patterned with DP method with nominal length of 80, 300, and 400 nm, and with conventional single patterning (SP) with nominal length of 350 nm. Each curve represents the results measured from 35 test structures.

Fig. 2-17 Cross-sectional SEM image of a fabricated device with nominal gate length of 120 nm. Practical length was measured to be 115 nm.

Fig. 2-18 (a) Transfer characteristics of NMOS control split biased at VD = 0.05V with various channel length ranging from 0.12 to 10 μm. All devices have the same width of 10 μm.

Fig. 2-18 (b) Transfer characteristics of NMOS control split biased at VD = 1.5V with various channel length ranging from 0.12 to 10 μm. All devices have the same width of 10 μm.

Fig. 2-19 (a) Transfer characteristics of NMOS and N-HALO splits with W/L=10 μm/120 nm.

Fig. 2-19 (b) Transfer characteristics of PMOS and P-HALO splits with W/L=10 μm/120 nm.

Fig. 2-20 (a) Output characteristics of NMOS and N-HALO splits with W/L=10 μm/120 nm.

Fig. 2-20 (b) Output characteristics of PMOS and P-HALO splits with W/L=10 μm/120 nm.

Fig. 2-21 (a) Threshold voltage as a function of gate length for NMOS and N-HALO splits.

Fig. 2-21 (b) Threshold voltage as a function of gate length for PMOS and P-HALO splits.

Fig. 2-22 (a) Drain induced barrier lowering (DIBL) as a function of gate length for NMOS and N-HALO splits.

Fig. 2-22 (b) Drain induced barrier lowering (DIBL) as a function of gate length for PMOS and P-HALO splits.

Fig. 2-23 (a) On-current at VGS = 1.5V and VD = 1.5V as a function of gate length for NMOS and N-HALO splits.

Fig. 2-23 (b) On-current at VGS = -1.5V and VD = -1.5V as a function of gate length for PMOS and P-HALO splits.

Chapter 3

A Comparison of Nano-scale Patterning Techniques

3.1 Introduction

Lithography has been playing a pivotal role in semiconductor manufacturing to keep the Moore’s Law in force since the inception of integrated circuits (IC). Actually the advancements of both lithography tools and associated processes have paved the way for the successful evolution of IC technology. Figure 3-1 displays the lithography roadmap for the potential solutions of dynamic random access memory (DRAM), micro processor unit (MPU) and Flash, respectively, predicted by the International Technology Roadmap for Semiconductors (ITRS) in 2012 [1], indicating that the continuous scaling of the devices is evitable for better performance and cheaper manufacturing cost. In recent years, 32 nm technology node employs the 193 nm immersion lithography tools for mass production [2]-[3]. However, the aforementioned advanced lithography modules accomplish a finer resolution at the expense of incredibly high tool and process costs which are usually not affordable in the university-based laboratories. As a result, a large part of academic studies focusing on exploring the properties and physics of nano-scale strcutures in the university-based laboratories need to count on an alternative method, such as electron-beam direct writing [4], ion-beam lithography [5], photoresist (PR) ashing [6-7], nanoimprint lithography (NIL) [8-11], or utilizing the bottom-up methods like metal-catalytic growth [12], solid-liquid-solid growth [13], oxide-assisted growth [14], etc.

Certainly specific issues are present to each of the aforementioned approaches.

The electron-beam and ion-beam lithography methods suffer from extremely low throughput as compared with the stepper-based photolithography, prohibiting them from being implemented in practical manufacturing [4-5]. The process development of NIL has been over one decade, but most of NIL processes are still slow and not proper to serve the purse of mass production. Some challenges, such as homogeneous heat transfer, recovery due to material time constant, and reduction of defects due to limited air dissolution or mechanical abrasion, are confronted as using thermal NIL [10-11]. For applying UV-NIL, fast curing speed, wetting, and nonreactive resists for enhancing the

lifetime of stamps are some of the major requests [9]. On the other hand, although the bottom-up approach like metal-catalytic growth provides more flexibility experimentally, it lacks good control over the dimensions, positioning, and alignment of nano-size structure. Plus, metal contamination [12] which would affect the device characteristics is also a concern.

From the viewpoints of both high-volume manufacturing and research, I-line steppers with mercury lamp as the exposure light source have been widely adopted for decades, and the correlated fabrication process is quite stable and well developed.

Nevertheless, the fatality of I-line lithographic process is the resolution around 300 nm owing to its long exposure wavelength of 365 nm, and it is not likely to directly accomplish sub-100 nm line patterns. Even if the PR ashing method is capable of pushing the resolution of conventional I-line process down to the nano-scale regime, a highly stable asher is very pivotal for the purposes of good reproducibility and uniformity of critical dimension (CD) of the printed patterns. In addition, the profile of ashed PR pattern would be distorted or even collapsed due to high aspect ratio after over-ashing process for finer line pattern, and such poor PR pattern would ruin the subsequent etching step. As far as process cost and throughput are concerned, the conventional I-line lithographic process combined with double-patterning technique (DP) [15] is developed as an alternative approach for researches of sub-100 nm nano-scale devices carried out in the university-based laboratories. Besides, DP technique and related processes combined with spacer patterning technique such as self-aligned double patterning (SADP) [16] and sidewall spacer quadruple patterning [17] are proposed as the potential solutions for lithography roadmap, as previously illustrated in Fig. 3-1. Consequently, we have focused on and compared two kinds of lithographic systems often applied in universities for research purpose, including electron beam tool and I-line stepper in this chapter. The merits and shortcomings of some techniques using two lithographic systems are discussed in terms of CD uniformity, line edge roughness (LER), throughput, and minimum line width. We have also developed an ameliorative DP technique with conventional I-line stepper to generate sub-60 nm photoresist (PR) patterns with the goal to fabricate asymmetric devices of nano-scale regime in this work. Finally, 45 nm gate length HfO2 dielectrics nMOSFETs with or without asymmetric channel doping were fabricated by the proposed I-line lithographic process and characterized as well.

3.2 Lithographic Experiments

3.2-1 Brief Illustrations of Lithographic Experiments

Before the execution of relative lithographic experiments discussed in this chapter, both test structure and observed area of line pattern are illustrated in Fig. 3-2 (a) for good comprehension of this section. Apparently, Fig. 3-2 (a) is applied for single-patterning schemes such as e-beam direct writing tools and PR ashing method.

On the other hand, double-patterning processes such as conventional and modified double-patterning techniques are illustrated in Fig. 3-2 (b). The observed zone is marked with a red dashed line over the active region of device for all lithographic experiments discussed as follows.

3.2-2 Experiments of Electron Beam Systems

Two types of electron beam direct writing tools, namely, LEICA WEPRINT 200 and ELIONIX ELS-7500EX are employed in this study. The former belongs to the shaped beam type and the latter is classified as Gaussian beam system. The exposure doses are around 7.2 µC/cm² at 40 keV with the shaped beam system, and 10 µC/cm² at 50 keV with the Gaussian beam system, respectively. In-line scanning electron microscope (SEM) technique was used to characterize the resultant photoresist (PR) patterns. Figure 3-3 depicts the in-line SEM images of isolated PR line patterns sampled randomly on a six-inch wafer exposed by the shaped beam system, while the images exposed by the Gaussian beam system are shown in Fig. 3-4. Due to the extremely long exposure process of the Gaussian beam system, the sampling area is limited to around 2 cm × 2 cm for one chip and totally we have accomplished three chip areas. As can be seen in Fig. 3-3, the line widths of resultant PR patterns distribute from 78 to 120 nm located at eight different dies of a wafer, while the Gaussian beam system exhibits the distribution from 69 to 111 nm in an area of 2 cm × 6 cm as shown in Fig. 3-4, indicating the Gaussian beam system is capable of generating finer line patterns.

3.2-3 Experiments of I-Line Stepper with PR Ashing Method

For all photolithographic steps carried out in this work, we used an I-line stepper (Canon FPA-3000i5+) to generate the PR patterns. First, the line width of PR pattern around 300 nm was implemented with modulating the exposure doses and focuses of

I-line stepper. To accomplish the finer line width of nano-scale regime, we adopted the PR ashing technique with oxygen plasma in a low process temperature environment to reduce the PR trimming rate and increase the process uniformity. The PR patterns were trimmed by oxygen plasma at RF power of 700 W for top electrode and 20 W for bottom electrode with oxygen flow rate of 35 sccm and chlorine flow rate of 20 sccm, and the process temperature and pressure were set to 65 ^oC and 80 mtorr, respectively.

The over-ashing PR patterns causing the LER degradation and/or the broken lines are shown in Fig. 3-5. Apparent broken lines, severe LER of PR patterns, and further the collapsed PR patterns suggest that the narrowest line patterns below 70 nm are not suitable to be generated directly by PR ashing method. Fig. 3-6 exhibits the in-line SEM images of isolated PR line patterns randomly sampled at eight different dies of a six-inch wafer generated by PR ashing method in a proper manner. The fluctuation of line width is about 56 nm, larger than 42 nm of the electron beam system, and the observed shortest line width is 84 nm, far thicker than the electron beam tool, and further the resultant PR patterns of less than 80 nm display terrible shapes, implying that PR ashing scheme gives self-imposed limitations on the implementation of finer line pattern generation.

3.2-4 Experiments of I-Line Stepper with Double Patterning Method

Another way to generate sub-100 nm line patterns through the conventional I-line process was done with the double patterning (DP) [15] technique. Figure 3-2 (b) shows the illustration of the two masks, denoted as G1 and G2, used for the DP method to define the gate electrode. The detailed process of DP technique basically is the same as that previously described in chapter 2. In brief, the process follows a lithography-etching-lithography-etching sequence which involves two separate masks, and the overlap regions of the two masks define the final etched structures on the wafer surface. In-line SEM images of randomly sampled line patterns at eight different dies of a six-inch wafer generated by DP method are depicted in Fig. 3-7. The overlay accuracy of the employed I-line stepper is about 45 nm which is one of the dominant factors for the CD deviation. As can be seen in the plots, the line widths of resultant PR patterns distribute from 81 to 126 nm, and the variation of 45 nm, mainly ascribed to the overlay accuracy of equipment, is better than PR ashing one.

3.2-5 Experiments of I-Line Stepper with Modified Double Patterning Method The modified DP method (denoted as Modified I-DP) is similar to the aforementioned DP method (denoted as I-DP). The unique feature of Modified I-DP distinct from previous DP method is the implementation of oxide hard mask trimming employed during the first gate pattern definition. Figure 3-8 illustrates the major process steps in the fabrication of nMOSFETs with symmetric channel doping by virtue of the modified I-DP technique. After the lithographic process of first gate pattern with mask G1, the anisotropic etching of the tetraethyl orthosilicate (TEOS) oxide hard mask layer was implemented by a reactive ion etch (RIE) step done by a Lam-TCP9400, as illustrated in Fig. 3-8 (b). Prior to the implementation of second gate patterning, the oxide hard mask layer trimming was executed as illustrated in Fig. 3-8 (c), followed by the removal of PR (G1) and a RIE of polycrystalline silicon (poly-Si) layer below. The second lithographic step with mask G2 was then employed to generate PR patterns which covered portion of both TEOS oxide hard mask layer and poly-Si layer remaining on the surface of the substrate [Fig. 3-8 (d)], followed by a RIE step to complete the final gate structure. By carefully controlling the lateral etching of the TEOS oxide hard mask layer in dilute HF solution as shown in Fig. 3-8 (c), the dimension of final line patterns [Fig. 3-8 (e)] could be further downscaled shorter than the conventional DP

3.2-5 Experiments of I-Line Stepper with Modified Double Patterning Method The modified DP method (denoted as Modified I-DP) is similar to the aforementioned DP method (denoted as I-DP). The unique feature of Modified I-DP distinct from previous DP method is the implementation of oxide hard mask trimming employed during the first gate pattern definition. Figure 3-8 illustrates the major process steps in the fabrication of nMOSFETs with symmetric channel doping by virtue of the modified I-DP technique. After the lithographic process of first gate pattern with mask G1, the anisotropic etching of the tetraethyl orthosilicate (TEOS) oxide hard mask layer was implemented by a reactive ion etch (RIE) step done by a Lam-TCP9400, as illustrated in Fig. 3-8 (b). Prior to the implementation of second gate patterning, the oxide hard mask layer trimming was executed as illustrated in Fig. 3-8 (c), followed by the removal of PR (G1) and a RIE of polycrystalline silicon (poly-Si) layer below. The second lithographic step with mask G2 was then employed to generate PR patterns which covered portion of both TEOS oxide hard mask layer and poly-Si layer remaining on the surface of the substrate [Fig. 3-8 (d)], followed by a RIE step to complete the final gate structure. By carefully controlling the lateral etching of the TEOS oxide hard mask layer in dilute HF solution as shown in Fig. 3-8 (c), the dimension of final line patterns [Fig. 3-8 (e)] could be further downscaled shorter than the conventional DP