Lithographic Experiments

3.2-1 Brief Illustrations of Lithographic Experiments

Before the execution of relative lithographic experiments discussed in this chapter, both test structure and observed area of line pattern are illustrated in Fig. 3-2 (a) for good comprehension of this section. Apparently, Fig. 3-2 (a) is applied for single-patterning schemes such as e-beam direct writing tools and PR ashing method.

On the other hand, double-patterning processes such as conventional and modified double-patterning techniques are illustrated in Fig. 3-2 (b). The observed zone is marked with a red dashed line over the active region of device for all lithographic experiments discussed as follows.

3.2-2 Experiments of Electron Beam Systems

Two types of electron beam direct writing tools, namely, LEICA WEPRINT 200 and ELIONIX ELS-7500EX are employed in this study. The former belongs to the shaped beam type and the latter is classified as Gaussian beam system. The exposure doses are around 7.2 µC/cm² at 40 keV with the shaped beam system, and 10 µC/cm² at 50 keV with the Gaussian beam system, respectively. In-line scanning electron microscope (SEM) technique was used to characterize the resultant photoresist (PR) patterns. Figure 3-3 depicts the in-line SEM images of isolated PR line patterns sampled randomly on a six-inch wafer exposed by the shaped beam system, while the images exposed by the Gaussian beam system are shown in Fig. 3-4. Due to the extremely long exposure process of the Gaussian beam system, the sampling area is limited to around 2 cm × 2 cm for one chip and totally we have accomplished three chip areas. As can be seen in Fig. 3-3, the line widths of resultant PR patterns distribute from 78 to 120 nm located at eight different dies of a wafer, while the Gaussian beam system exhibits the distribution from 69 to 111 nm in an area of 2 cm × 6 cm as shown in Fig. 3-4, indicating the Gaussian beam system is capable of generating finer line patterns.

3.2-3 Experiments of I-Line Stepper with PR Ashing Method

For all photolithographic steps carried out in this work, we used an I-line stepper (Canon FPA-3000i5+) to generate the PR patterns. First, the line width of PR pattern around 300 nm was implemented with modulating the exposure doses and focuses of

I-line stepper. To accomplish the finer line width of nano-scale regime, we adopted the PR ashing technique with oxygen plasma in a low process temperature environment to reduce the PR trimming rate and increase the process uniformity. The PR patterns were trimmed by oxygen plasma at RF power of 700 W for top electrode and 20 W for bottom electrode with oxygen flow rate of 35 sccm and chlorine flow rate of 20 sccm, and the process temperature and pressure were set to 65 ^oC and 80 mtorr, respectively.

The over-ashing PR patterns causing the LER degradation and/or the broken lines are shown in Fig. 3-5. Apparent broken lines, severe LER of PR patterns, and further the collapsed PR patterns suggest that the narrowest line patterns below 70 nm are not suitable to be generated directly by PR ashing method. Fig. 3-6 exhibits the in-line SEM images of isolated PR line patterns randomly sampled at eight different dies of a six-inch wafer generated by PR ashing method in a proper manner. The fluctuation of line width is about 56 nm, larger than 42 nm of the electron beam system, and the observed shortest line width is 84 nm, far thicker than the electron beam tool, and further the resultant PR patterns of less than 80 nm display terrible shapes, implying that PR ashing scheme gives self-imposed limitations on the implementation of finer line pattern generation.

3.2-4 Experiments of I-Line Stepper with Double Patterning Method

Another way to generate sub-100 nm line patterns through the conventional I-line process was done with the double patterning (DP) [15] technique. Figure 3-2 (b) shows the illustration of the two masks, denoted as G1 and G2, used for the DP method to define the gate electrode. The detailed process of DP technique basically is the same as that previously described in chapter 2. In brief, the process follows a lithography-etching-lithography-etching sequence which involves two separate masks, and the overlap regions of the two masks define the final etched structures on the wafer surface. In-line SEM images of randomly sampled line patterns at eight different dies of a six-inch wafer generated by DP method are depicted in Fig. 3-7. The overlay accuracy of the employed I-line stepper is about 45 nm which is one of the dominant factors for the CD deviation. As can be seen in the plots, the line widths of resultant PR patterns distribute from 81 to 126 nm, and the variation of 45 nm, mainly ascribed to the overlay accuracy of equipment, is better than PR ashing one.

3.2-5 Experiments of I-Line Stepper with Modified Double Patterning Method The modified DP method (denoted as Modified I-DP) is similar to the aforementioned DP method (denoted as I-DP). The unique feature of Modified I-DP distinct from previous DP method is the implementation of oxide hard mask trimming employed during the first gate pattern definition. Figure 3-8 illustrates the major process steps in the fabrication of nMOSFETs with symmetric channel doping by virtue of the modified I-DP technique. After the lithographic process of first gate pattern with mask G1, the anisotropic etching of the tetraethyl orthosilicate (TEOS) oxide hard mask layer was implemented by a reactive ion etch (RIE) step done by a Lam-TCP9400, as illustrated in Fig. 3-8 (b). Prior to the implementation of second gate patterning, the oxide hard mask layer trimming was executed as illustrated in Fig. 3-8 (c), followed by the removal of PR (G1) and a RIE of polycrystalline silicon (poly-Si) layer below. The second lithographic step with mask G2 was then employed to generate PR patterns which covered portion of both TEOS oxide hard mask layer and poly-Si layer remaining on the surface of the substrate [Fig. 3-8 (d)], followed by a RIE step to complete the final gate structure. By carefully controlling the lateral etching of the TEOS oxide hard mask layer in dilute HF solution as shown in Fig. 3-8 (c), the dimension of final line patterns [Fig. 3-8 (e)] could be further downscaled shorter than the conventional DP method. Furthermore, the Modified I-DP method would achieve sub-60 nm line patterns without the risk of collapsed PR patterns and the CD non-uniformity issue encountered in PR ashing technique. In-line SEM images of randomly sampled line patterns at eight different dies of a six-inch wafer generated by the modified DP method are depicted in Fig. 3-9. The line widths of resultant PR patterns distribute from 42 to 93 nm, confirming the resolution capability of the modified DP method in terms of sub-50 nm line pattern generation at the expense of 51 nm variation. In addition, the variation of 51 nm, mainly ascribed to the inherent overlay accuracy of equipment plus the uniformity of TEOS oxide hard mask trimming process, is a little worse than conventional DP method (45 nm), albeit still better than PR ashing scheme (63 nm). In-line SEM images of dense line patterns generated by the modified DP method compared with conventional I-line single patterning process are illustrated in Fig. 3-10. Here the conventional single patterning and the modified double patterning are denoted as I-SP and Modified I-DP, respectively. We find Modified I-DP can achieve almost half pitch of I-SP and generate line widths of about 32 nm.

3.3 Devices Fabrication

After confirming the feasibility of the present Modified I-DP technique, we have also implemented this technique on the practical fabrication of nano-scale n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) with or without asymmetric channel doping architecture. Figure 3-8 illustrates the major process steps in the device fabrication. Local oxidation of Si (LOCOS) scheme was first used for device isolation. P-type well was then formed by BF2+

implantation with energy of 70 keV and dose of 1×10¹³ cm^-2, followed by a drive-in anneal step at 1100 ^oC. Next, channel stop implantation was performed by implanting BF₂⁺ (120 keV, 4×10¹³ cm^-2), followed by wet oxidation to form 450 nm-thick field oxide. Anti-punchthrough (APT) and threshold voltage (V_th) adjustment implantations were performed individually by implanting B⁺ (70 keV, 2×10¹² cm^-2) and BF₂⁺ (90 keV, 1×10¹³ cm^-2), respectively.

Afterwards, 7 nm-thick HfO₂ was deposited as the gate dielectric by an ALD system with 1 nm-thick interfacial oxide layer fabricated by the rapid thermal oxidation at 500

oC for 10 seconds. Gate electrode with thickness of about 100 nm-thick in situ phosphorus-doped poly-Si was deposited, followed by the deposition of 50 nm low pressure chemical vapor deposition (LPCVD) TEOS oxide layer as hard mask as shown in Fig. 3-8 (a). After gate definition with the modified DP method as previously described [Figs. 3-8 (b), (c), (d) and (e)], halo implantations were executed by implanting BF2+

(50 keV, 5×10¹² cm^-2, tilt = 45°) embedded symmetrically in both source and drain (S/D) junctions for the symmetric S/D doping split (denoted as Symmetric Halo). In contrast, the asymmetric S/D doping split (denoted as Asymmetric Halo) could be implemented by embedding halo doping only in the source side prior to the second lithographic step with mask G2. Shallow S/D extensions were formed by implanting As⁺ (5 keV, 1×10¹⁵ cm^-2). After forming a 100 nm-thick TEOS sidewall spacer, deep S/D junctions were formed by implanting As⁺ (20 keV, 2×10¹⁵ cm^-2) and P31+

(10 keV, 5×10¹⁵ cm^-2) in sequence, and then rapid thermal anneal (RTA) was carried out in a nitrogen ambient at 1000 ^oC for 10 seconds to activate dopants in the gate and S/D junctions, as depicted in Fig. 3-8 (f). Finally, 680 nm-thick TiN/AlSiCu/TiN/Ti metallization was carried out in a PVD system to form the metal pads, and then the processing steps were completed with a forming gas anneal at 400 °C for 30 minutes. The overall implantation conditions used in the device fabrication were arranged as shown in Table 3-1. Figure 3-11 depicts the cross-sectional transmission

electron microscopic (TEM) image of a fabricated HfO₂ dielectric nMOSFET, and gate length is about 45 nm. Finally, electrical characteristics were performed using an Agilent 4156 system.

3.4 Results and Discussion

3.4-1 Performance Comparison of Lithographic Techniques

The lithographic throughput comparison among aforementioned processes with electron beam tools or I-line stepper is illustrated in Fig. 3-12, and further the correlative process time versus device throughput is shown in Fig. 3-13. For good comprehension of this section, we name all lithographic techniques as follows: “Shaped beam” represents shaped beam system of electron beam tool, “Gaussian beam” stands for another electron beam tool employed with discrete Gaussian distribution as electron beam dose, “I-line SP” represents the conventional single-patterning scheme with I-line stepper, “PR-ashing” represents the conventional I-line process with PR ashing technique, “I-line DP” represents the double-patterning technique with I-line stepper, and “Modified I-DP” represents the modified double-patterning technique with I-line stepper. From both Figs. 3-12 and 3-13, apparently we find out that although the throughput is cut in half for I-line process when conventional DP scheme and Modified I-DP method are employed, it is still approximately 100 and 50000 times higher than the throughput of the shaped beam process and the Gaussian beam process, respectively. In addition, the throughput of PR ashing scheme is similar to that of the DP method due to 0.7 nm/s PR etching rate of oxygen plasma trimming. Figure 3-14 illustrates the CD distributions of I-DP, Modified I-DP, PR ashing method, Shaped beam and Gaussian beam splits. Among these CD distributions, both electron beam tools share the best uniformity of CD at the expense of very low throughput. The CD distribution of PR ashing is obviously wider than the others, hence a highly stable asher for good reproducibility and uniformity of CD of the printed pattern is essential. Moreover, the oxide hard mask trimming of the modified I-DP process is capable of pushing the CD down to sub-60 nm without compromising its deviation as compared with conventional DP method. In summary, the uniformity of CD, throughput, LER and minimum line width of the aforementioned lithographic processes are quantitatively compared and organized in Table 3-2. From this table, the DP technique and the modified DP

technique have above-average performance, and the minimum line width of isolated line pattern can be further downscaled to 45 nm by virtue of the proposed modified DP scheme without sacrificing other performances.

3.4-2 Devices Characteristics

After the discussion about performance comparison of lithographic techniques, we have not only comprehended some lithographic features but confirmed the feasibility of the proposed Modified I-DP scheme as well. The following are the fundamental electrical characteristics of the fabricated devices we will pay attention to. Here we define the junction fabricated with single halo implantation in the Asymmetric Halo split as the source side. First of all, the transfer characteristics of nMOSFETs measured at VD= 0.05V with gate length (L) of 10 μm and gate width (W) of 10 μm are illustrated in Fig. 3-15 (a), where both devices have the same architecture with symmetric channel doping. The difference of fabricated devices is in the applied materials of gate dielectrics, i.e., one split is thermal N2O oxide with thickness of about 2.5 nm denoted as N2O dielectric, and another split is 7 nm-thick HfO2 with 1 nm-thick interfacial oxide layer denoted as HfO2 dielectric. The output characteristics of nMOSFETs with gate length of 10 μm and gate width of 10 μm measured at VGS-Vth = 0 ~ 2 V, step= 0.4 V, and VD = 0 ~ 2 V are illustrated in Fig. 3-15 (b). As can be seen in Figs. 3-15 (a) and (b), the HfO2 dielectric split displays about 130 mV/dec subthreshold swing, worse than the 80 mV/dec for the N₂O dielectric split, and the HfO₂ dielectric split exhibits poor current drivability apparently. Two shortcomings can be ascribed to the extremely awful interface between gate dielectric and channel, and further it ruins not only device switching property, but other performance such as transconductance as shown in Fig.

3-16. The HfO₂ dielectric split shows a normalized transconductance of 1.34×10^-7 μS/μm, 10 times lower than the N2O dielectric split, and is consistent with the aforementioned difference of output characteristics as depicted in Fig. 3-15 (b).

Therefore a good interface property is critical to device performance. Figure 3-17 shows transfer characteristics of two gate dielectrics splits measured at V_D = 0.05 and 2 V with gate width of 10 μm and the same symmetric channel doping architecture, both with 45 nm gate length. Even though the halo implantation was implemented in the N₂O dielectric split, severe punchthrough current resulted from poor gate controllability over channel region and serious penetration of depletion region from drain to source side,

leads to delinquency of device operation. In contrast with the N₂O dielectric split, the HfO₂ dielectric split exhibits better immunity to short-channel effect in terms of successful suppression of both surface and bulk punchthrough currents. Thanks to the implementation of HfO2 dielectric, stronger gate controllability is achieved with the aid of thinner capacitance equivalent thickness (CET) of HfO2 dielectric and is credited for the successful operation of such short-channel device.

Figures 3-18 (a) and (b) illustrate the transfer and output characteristics of nMOSFETs with symmetric and asymmetric S/D doping configuration, respectively, The device dimension is gate length of 45 nm and gate width of 10 μm. The Symmetric Halo split exhibits better suppression of short channel effects (SCEs) including less drain induced barrier lowering (DIBL) and lower off-state leakage current, even biased under a high drain voltage of 2 V. This is ascribed to the fact that the symmetrical halo implant increases the local substrate doping concentration and reduces the depletion width at channel edges, and therefore the lowering in surface potential barrier height with a higher drain voltage is relieved. However, the downside is the worse current drivability as compared with the Asymmetric Halo split. Thanks to inherently asymmetric S/D doping, the Asymmetric Halo split suffers from less side effect of halo doping as compared with bilateral halo doping architecture, and therefore contributes to a 20% enhancement of driving current as illustrated in Fig. 3-18 (b). In addition, the 20% increment of driving current may not be totally contributed by unilateral halo doping architecture while the variation of CET or gate capacitance could be another possible contributor discussed as follows. Prior to the discussion of gate capacitance of HfO2 dielectric, we have to choose the suitable device dimension for capacitance measurement. Figures 3-19 (a), (b) and (c) exhibit the transfer characteristics including gate current components of three kinds of device sizes (W/L = 50 μm/50 μm, 20 μm/20 μm, and 10 μm/10 μm) measured at VD = 0.05 V. Gate current comparable to or even larger than drain current can be distinguished from Figs. 3-19 (a) and (b), and such unbelievable gate leakage current is attributed to the crystallization of HfO2 film after dopant activation annealing process, even if the interfacial oxide layer was artificially introduced to the device fabrication. The crystallization temperature of HfO2 is relatively low (i.e., around 300~400 ^oC) and its thermal stability is not good as well [18], and therefore 1000 ^oC RTA process certainly is sufficient to result in a crystallized HfO2

dielectric. Besides, gate leakage current issue is relieved with downscaling the device size as illustrated in Fig. 3-19 (c). From this plot, the gate current apparently decreases

with gate length of 10 μm and gate width of 10 μm, implying that larger channel area has higher possibility of the generation of crystallized leakage paths in HfO₂ dielectrics.

In addition, the artificial interfacial oxide is not robust as expected, and it leads to gate leakage current as well. In short, we selected devices with W/L = 10 μm/10 μm for the capacitance measurement owing to the gate leakage current issue mentioned above. The capacitance-voltage characteristics of the HfO2 dielectric split randomly sampled at eleven different dies of a six-inch wafer with gate length of 5 μm and gate width of 10 μm are shown in Fig. 3-20. The measurement frequency is 100 kHz. Here we measured the two test samples with gate lengths of 5 μm and 10 μm for the same gate width of 10 μm, and subtracted the capacitance of 5 μm-sample from that of 10 μm-sample in order to eliminate the parasitic capacitance. As can be seen, the normalized capacitances distribute from 2.83 to 3.03 μF/cm², and the variation of 8 % would be likely ascribed to the uniformity of rapid-thermal-oxidation (RTO) process suspected for the interfacial oxide growth. For the ALD HfO2 dielectric, we believe the fluctuation of capacitance is derived mainly from the variation of interfacial oxide thickness induced by rapid thermal process, and the delicate interfacial oxide possibly came from RTO process as well.

Figure 3-21 shows the threshold voltage of the fabricated devices as a function of the gate length with W = 10 μm. The threshold voltage is defined as the gate voltage at drain current of (W/L) · 10nA biased with a small drain voltage (V_D) of 0.05 V. As described in Fig. 3-18, halo implantation effectively improves the SCEs in MOSFETs, however, it has some drawbacks including the drain-substrate coupling, the degradation of driving current and enhanced reverse-short-channel-effect (RSCE). The Symmetric Halo split depicts severer RSCE than the Asymmetric Halo split because bilateral halo increases doping distribution near the S/D edges of the channel, and therefore results in a locally higher threshold voltage. In addition, as the gate length downscales to below 100 nm, the threshold voltage of Symmetric Halo device is slight larger than Asymmetric Halo device. Owing to the sufficiently short channel comparable to the width of channel depletion region, the portion of the sharing of the charges in the channel depletion region with the S/D junctions becomes much significant and thus results in threshold voltage rolling. Hence the inherently unilateral halo doping of Asymmetric Halo device exhibits more threshold voltage rolling as compared with the Symmetric Halo counterpart. The current drivability (Ion) as a function of the gate length with W = 10 μm biased at gate over-drive voltage (VGS-Vth) of 2 V and drain voltage

(V_D) of 2 V is shown in Fig. 3-22. The Asymmetric Halo device exhibits higher driving current than Symmetric Halo device, indicating the benefit of adopting asymmetric structure. Even with the larger subthreshold leakage current, the Asymmetric device can

(V_D) of 2 V is shown in Fig. 3-22. The Asymmetric Halo device exhibits higher driving current than Symmetric Halo device, indicating the benefit of adopting asymmetric structure. Even with the larger subthreshold leakage current, the Asymmetric device can