Results and Discussion

2.4-1 End Point Detection Issue

During device fabrication with DP technique, a major issue related to the ineffectiveness of end point detection (EPD) in the second poly-Si etch step was found.

Figure 2-5 shows the evolution of optical emission signal intensity during the second poly-Si etch step on a test wafer. Normally the end point should be detected at around 20 seconds after the turning on of plasma, but this did not happen instead the signal remained stable. Moreover, the signal intensity appeared to be much weaker than that recorded during the first poly-Si etch step. Since the signal intensity is related to the etch by-products [14], which is believed to be related to the layout design of mask G1.

In the original version of G1 mask, over 90% of the blanket poly-Si area is not covered by the PR and is etched off in the first poly-Si etch step, and consequently the end point (defined as the moment when the intensity drops to 90% of the peak intensity) can be easily detected in the main etch stage of the first etch step. However, with the scanty poly-Si left during the second etch, only a very weak optical signal is detectable, causing the failure of EPD.

Besides, owing to the ultrathin gate oxide, EPD failure may cause the breakthrough

of the gate oxide, Si recess in the substrate, and further result in device failure. Figure 2-6 illustrates the cross-sectional scanning electron microscopy (SEM) image of a MOSFET showing a recess in the Si substrate at the right side of the gate, an indication of the damage induced in the second etching process. When this happens, the devices exhibit very leaky characteristics and are no longer suitable for practical application.

The aforementioned issue could be resolved by modifying the layout design of the mask G1. This was implemented by inserting some dummy patterns to the layout of the mask G1 to increase the remaining area of the poly-Si film after the first etching step. These dummy patterns removed in the second etching step could contribute more etch by-products and increase the optical signal for effective EPD. The feasibility of the modified mask design is evidenced by the EPD results recorded during the first and second poly-Si gate etching steps, as shown in Figs. 2-7(a) and 2-7(b), respectively. In the two etching steps, EPD could both be successfully carried out. To further highlight the effectiveness of the new layout design, the in-line SEM pictures of the poly-Si line after the second etch step with original and modified layout are shown in Figs. 2-8(a) and 2-8(b), respectively. An obvious etch-induced damage region, corresponding to the Si recess region shown in Fig. 2-6, is observed at the right side of the gate in Fig. 2-8(a).

In Fig. 2-8(b), with the modified layout, such damage could be completely eliminated.

2.4-2 Feasibility of Double Patterning Technique

The e-beam lithography suffers from a very low throughput, as stated in Sec. 2.1.

Figure 2-9 illustrates the throughput comparison between processes with e-beam tool (LEICA WEPRINT 200) and I-line stepper (Canon FPA-3000i5+). The patterning method with e-beam tool is denoted as Shaped beam. Conventional single exposure with I-line stepper and DP scheme with I-line stepper are denoted as I line-SP and I line-DP, respectively. We could find that, though the throughput is cut by half for I-line process when DP scheme is employed, it is still about 100 times the throughput of the e-beam process, implying that I line-DP possesses both high throughput and nano-scale pattern generation capability.

Before confirming the feasibility of DP technique in this section, both test structure and observed area of line pattern are illustrated in Fig. 2-10, and the observed zone is marked with a red dashed line over the active region of the device. Figure 2-11 shows the after-etching-inspection (AEI) images, with the designed value larger than 100 nm,

recorded by in-line SEM. Here, L_ovp is the nominal designed length of mask layout and L_poly is the practical physical length through lithography and etching processes. Figure 2-11 (a) shows in-line SEM image of a patterned poly-Si line with nominal line width of 500 nm and the measured line width is 498 nm. In-line SEM image of a patterned poly-Si line with nominal line width of 400 nm is illustrated in Fig. 2-11 (b) and the measured line width is 390 nm. Figure 2-11 (c) depicts in-line SEM image of a patterned poly-Si line with nominal line width of 300 nm and the measured line width is 294 nm. In-line SEM image of a patterned poly-Si line with nominal line width of 200 nm is exhibited in Fig. 2-11 (d) and the measured line width is 214 nm. In contrast with Fig. 2-11, Figs. 2-12, 2-13 and 2-14 show the in-line SEM images of AEI with Lovp less than 100 nm. In-line SEM images of patterned poly-Si lines located at eight different dies of a wafer with nominal line width of 100 nm are shown in Fig. 2-12, and the measured line widths are distributed from 81 nm to 126 nm. Figure 2-13 illustrates in-line SEM images of patterned poly-Si lines located at eight different dies of a wafer with nominal line width of 80 nm, and the measured line widths are distributed from 60 nm to 103 nm. Next, the minimum L_ovp of mask layout is 50 nm, and in-line SEM images of patterned poly-Si lines randomly located on a wafer are depicted in Fig. 2-14.

Obviously discontinuous line patterns can be discovered in the active regions of devices even if L_poly of these disabled patterned poly-Si lines can achieve 25 nm. The aforementioned L_poly values displayed in Figs 2-12, 2-13 and 2-14 are quite reasonable as far as the overlay accuracy of the I-line stepper is concerned. As shown in Table 2-3 provided by the vendor, the overlay accuracy is 45 nm at most. This implies that the gate length designed below 80 nm is out of control and difficult to reproduce, which is consistent with Fig. 2-14. Anyway, the present DP method is useful for generation of line patterns down to 80 nm with reliable control of critical dimensions, as shown in Fig.

2-13.

The controllability of critical dimension (CD) is checked by a collection of the linewidth of patterned poly-Si gates measured by in-line SEM, as depicted in Fig. 2-15.

As can be seen in this figure, the dimensions of the printed polygates are close to those of the mask patterns. Figure 2-16 shows the cumulative plots of the measured poly-Si gates with nominal lengths of 80, 300, and 400 nm, patterned with the present DP technique. Also shown in the figure are the results of poly-Si gates with nominal length of 350 nm patterned with conventional I-line technique. In the figure each curve represents measured data obtained from 35 test samples distributed across the test wafer.

The results clearly demonstrate the capability of this approach of not only shrinking the gate length beyond the resolution limit of single patterning technique (>300 nm) but also achieving a better dimension control as compared with conventional I-line process.

Even with a much smaller gate dimension, the distribution in the measured gate width of the DP-patterned lines is obviously tighter than that of the conventional I-line method.

Since the feature sizes of G1 and G2 patterns are much larger than the resolution limit of the I-line stepper, the CD variation is strongly dependent on the alignment accuracy of the exposure tool. According to the specifications of the employed stepper as shown in Table 2-3, the overlay accuracy (3σ) is about 45 nm. This value is close to the deviation of the measured data (51 nm) with the DP technique shown in Figs. 2-15 and 2-16. In other words, the overlay accuracy of the exposure tool sets the limit for the CD control of the present approach. This may result in a noticeable variation in device characteristics as its dimensions are small. Fortunately, such concern can be relieved with a modification in process steps to tailor the device structure. An example is the implementation of asymmetrical S/D, which is characterized and discussed in Chapter 4.

Finally, the profile of an etched poly-Si gate pattern of a fabricated device recorded by cross-sectional SEM is shown in Fig. 2-17. The image obviously indicates that a gate length of about 115 nm with the designed L_ovp of 120 nm is achieved, further confirming the feasibility of the proposed I-line DP lithographic technique.

2.4-3 Devices Characteristics for n-MOSFETs and p-MOSFETs

Figures 2-18 (a) and (b) show the transfer characteristics of NMOS control devices with various channel length under different drain biases. When the dimensions of devices scale down from 10 μm to 0.12 μm, severe bulk punchthrough current occurs and causes the degradation of subthreshold characteristics in control samples, resulting in subthreshold leakage current of two orders larger than long-channel devices at V_GS = 0 V. The above-mentioned bulk punchthrough current induced degradation of subthreshold characteristics can be comprehended with the charging sharing model [15-16], sharing the charges in the channel depletion region with S/D junctions. For a long-channel device, there is little impact of S/D depletion on the channel potential due to its remote channel from source to drain area. In contrast with long-channel case, the short-channel counterpart, comparable to its depletion-width in the channel region, suffers from significant effect of charges sharing with S/D junctions, causing the Vth

lowering. Furthermore, such phenomenon becomes severer as a high drain bias applied to the short-channel device, and causes further penetration of drain-side depletion region into the channel, resulting in lowering of the surface potential barrier of the channel.

Therefore, when device size is scaling down, the gate controllability becomes weaker as shown in Fig. 2-18 (b).

Figures 2-19 (a) and (b) illustrate the comparison of subthreshold characteristics with channel length (L) of 10 μm and channel length (W) of 0.12 μm for n-MOSFETs and p-MOSFETs, respectively. The implementation of halo implant efficiently relieves the aforementioned degradation of subthreshold characteristics in terms of reducing off-state leakage current (drain current at gate voltage of 0 V and VD = +/-1.5 V) of two orders lower than control samples, improving subthreshold swing and increasing Vth as clearly shown in those figures. Halo implant was adopted to increase the local substrate doping concentration and consequently relax the penetration of drain-side depletion region into the channel. Especially, the lowering in surface potential barrier height under a high drain bias is improved as well. However, you can not sell the cow and drink the milk. The recovery of gate controllability over the short-channel effect by using halo scheme is at the expense of device performance such as transconductance and current drivability degradation. Figures 2-20 (a) and (b) show the output characteristics of both n- and p-MOSFETs with W/L = 10 μm/0.12 μm and VGS-V_th = 0 ~ 2 V. A drain current degradation of about 13% is found as the halo implant is executed. Such degeneracy is ascribed to the RSCE induced V_th increment and accordingly ruined the current drivability.

Threshold voltage as a function of channel length for both n- and p-MOSFETs with W = 10 μm are shown in Figs. 2-21 (a) and (b). The threshold voltage is defined as the gate voltage at drain current of (W/L) · 10nA biased with a small drain voltage (V_D = +/- 0.05 V). As can be seen in the plots, both N-HALO and P-HALO splits exhibit obviously the reverse-short-channel-effect (RSCE) because halo increases doping distribution near the S/D edges of the channel, and therefore results in a locally higher threshold voltage. Figures 2-22 (a) and (b) depict drain induced barrier lowering (DIBL) as a function of channel length for both n- and p-MOSFETs with W = 10 μm. It is apparently identified that halo scheme indeed relieves the lowering in surface potential barrier height under a high drain bias in terms of reducing DIBL of N-HALO and P-HALO splits as compared with the control counterparts. Nonetheless, one of the side effects of halo is the degenerate current drivability as illustrated in Fig. 2-23. On-current

(I_on) as a function of channel length for both n- and p-MOSFETs with W = 10 μm is shown in Figs. 2-23 (a) and (b), respectively. From the plots, the I_on of the halo devices is about 13% smaller than that of control devices, once more indicating the degradation of driving current with the adoption of halo.