Device Fabrication and Experiment

5.2-1 Junctionless NWFETs

Figure 5-1 briefly illustrates the key fabrication process flow of the proposed GAA JL NWFET. First, a sandwich stack of nitride/tetraethyl orthosilicate (TEOS) oxide/nitride layers was sequentially deposited and then patterned on a six-inch silicon substrate capped with a 200-nm-thick thermally grown oxide. Next, the formation of sub-100-nm cavities underneath both sides of the top nitride was implemented by selective lateral etching of the TEOS oxide layer using diluted hydrofluoric (HF) solution (HF:H2O = 1:100) as shown in Fig. 5-1 (a). The tilted scanning electron microscopic (SEM) images before and after cavity formation are illustrated in Fig. 5-2.

An indistinct cavity was formed after 20-second etching time. In contrast with 20-second etching time, with 60-second etching time, a distinguished shape of cavity was formed and served as the mold for the formation of NW channels. An in situ phosphorus-doped poly-Si layer was then deposited using SiH4 of 0.49 slm and PH3 of 15 sccm in the low-pressure chemical vapor deposition (LPCVD) system at 550 ^oC and 600 mtorr onto the nano-cavity [Fig. 5-1 (b)]. The doped poly-Si film was then patterned and etched in a transformer-coupled plasma reactor using Cl₂/HBr gases to define NW doped channels (denoted as JL) and S/D regions simultaneously for the purpose of realizing the structure without junctions (i.e., n⁺-n⁺-n⁺), as illustrated in Fig.

5-1 (c). Note that the conventional inversion-mode (IM) counterparts (i.e., n⁺-i-n⁺) were also processed along with a similar flow but using an undoped poly-Si film as the channel (denoted as IM), while the S/D regions were formed with the same in situ phosphorus-doped poly-Si layer as in the JL devices. In addition, the in situ doping

process was chosen to yield a uniform resistivity distribution of around 2.7 mΩ·cm on a six-inch wafer and has good reproducibility, and further, has been commonly employed as the material of gate electrode. To fulfill the GAA structure, the sandwich stack comprising nitride/TEOS oxide/nitride layers was sequentially removed by wet-etching process in order to suspend the NW channels, as depicted in Fig. 5-3 with various sizes of NWs. As can be seen in the plots recorded by in-line SEM, different sized NW channels, including tiny, mid-sized and large-sized NWs, were exposed before the gate stack formation. Afterwards, the high-κ/metal gate stack structure was formed by using an atomic-layer deposition (ALD) system to deposit 10-nm-thick Al2O3 and 10-nm-thick TiN films conformally onto the NW channel, as shown in Fig. 5-1 (d).

Note that the final thickness of the TiN gate electrode is 150 nm by sputtering another 140-nm-thick TiN film. Some wafers skipping the deposition of Al2O3, adopted the LPCVD TEOS oxide as gate dielectric layer. After the definition of gate electrode, the deposition of PECVD TEOS passivation layer and AlSiCu metallization procedure, the fabrication of JL and IM NW devices were accomplished, as illustrated in Fig. 5-1 (e).

Figure 5-1 (f) shows the schematic top-view layout, indicating the location of NW channels.

Figure 5-4 depicts the cross-sectional high-resolution transmission electron microscopic (HRTEM) image of a fabricated GAA JL NWFET with the TEOS oxide/TiN gate stack, and an NW size of around 12 nm in thickness (T) and 23 nm in width (W). Here we performed the fast Fourier transform technique on the HRTEM image to acquire diffraction pattern revealed in the inset, indicating that the monocrystalline structure of the Si grain with [110] orientation. According to Wada’s work [23], poly-Si with higher n-type doping concentration exhibits larger grain size.

Therefore, the fabrication of poly-Si NWFETs would benefit by the adoption of an n⁺-poly-Si material with the enhanced crystallinity, inferring that it is one merit of JL scheme. The cross-sectional TEM images of fabricated GAA JL NWFETs with the Al2O3/TiN gate stack structure and three different sizes of NW channels are shown in Fig. 5-5. As can be seen in these images, the smallest one is around 10 nm in thickness and 15 nm in width, while other larger NWs are 75 nm × 30 nm denoted as mid-sized JL and 152 nm × 74 nm denoted as large-sized JL, respectively. In addition, Hall measurements were performed on a blanket in situ doped poly-Si thin film of 300 nm with two kinds of PH3 flow rates, as recorded in Table 5-1. It should be noted that the

nominal doping concentrations are 6 × 10²⁰ cm^-3 and 1 × 10²⁰ cm^-3 for the n⁺-poly-Si gate and the NW channels, respectively. However, the practical active carrier concentration in the NW channels of the fabricated devices would be much lower than the result of Hall measurements. According to a report by Fred Lacy [24], the electrical resistivity of a thin film will increase as the dimensions of the film become sufficiently small owing to the reduced mean free path of conduction carriers. On the other hand, the effects of donor deactivation and phosphorous segregation occurring in the NW channel are other culprits of lower carrier concentration [25, 26].

5.2-2 Junctionless SONOS Nonvolatile memory Devices

The process flow of poly-Si NW SONOS memory device with JL scheme is similar to that of the previously described JL GAA NWFET, and is illustrated in Fig. 5-6.

Here we describe some key process parameters in this section. A 100-nm-thick in situ phosphorous doped poly-Si layer, which was carried out using mixed gases of SiH₄ and PH₃, was adopted as the channel material of the JL structure (i.e., n⁺-n⁺-n⁺), as shown in Fig 5-6 (c). The doping concentration can be varied by simply adjusting the PH₃ flow rate such as 15 sccm for lighter doping and 30 sccm for heavier doping, while keeping the same SiH4 flow rate of 0.49 slm. To implement the GAA configuration, the top-nitride/bottom-nitride and TEOS oxide layers were removed by hot H3PO4 and HF solution, respectively, to expose the NW channels, as depicted in Fig. 5-6 (d). To fulfill the SONOS structure, a gate dielectric stack of blocking oxide/trapping nitride/tunneling oxide (ONO) with thicknesses of 12/7/3 nm was deposited by LPCVD, as illustrated in Fig. 5-6 (e). In comparison, conventional IM memory devices (i.e., n⁺-i-n⁺) with undoped poly-Si NW channels having the same ONO stack were also fabricated. Afterwards, an in situ phosphorous doped n⁺-poly-Si layer was deposited using SiH4 of 0.49 slm and PH3 of 100 sccm by LPCVD and then patterned to serve as the gate electrode, as shown in Fig. 5-6 (f). On the other hand, the omega-shaped gate (Ω-gate) configuration was fabricated as well by retaining a portion of the bottom- nitride during the removal of the sandwich stack comprising nitride/TEOS oxide/nitride layers. Figure 5-7 illustrates two schematic gate structures (GAA/Ω-gate) implemented in our JL-SONOS memory cells for better comprehension.

Figure 5-8 (a) shows the top-view SEM image of a fabricated JL NW memory device and the channel length is defined as the spacing between the S/D regions. The cross-sectional TEM image of the NW channel with GAA structure is shown in Fig. 5-8

(b) and the dimension of NW is about 11 nm × 6 nm, apparently enclosed by the ONO gate stack and poly-Si gate. According to our original process design of nano-cavity formation, the cross section of the poly-Si NWs is supposed to be rectangular in shape.

Nonetheless the observed NW exhibits a nearly elliptic profile. Because our NW channels experienced a series of wafer cleaning and etching steps proceeded in chemical solutions through device fabrication, the NW’s corners were rounded, eventually leading to an elliptic shape. In contrast with the GAA configuration, the cross-sectional TEM image of NW channel with Ω-gate structure is shown in Fig. 5-8 (c), indicating that the cross section of the NW is about 12 nm × 6.5 nm. For the purpose of better understanding in discussing device characterization, the splits of fabricated JL SONOS memory cells are listed in Table 5-2. Note that the NW memory devices with channel length of 0.4 μm were used for the analyses of both electrical and memory characteristics.

5.2-3 Three-Dimensional Multilayer-Stacked Junctionless NWFETs

The Illustration of the key steps for building three-dimensional (3-D) multilayer stacked JL poly-Si NW device, similar to that of the previously described JL GAA NWFET, is displayed in Fig. 5-9. Here we describe some key process parameters in this section. The sequential depositions of 3-level nitride (SiN)/TEOS oxide stacked layers were implemented to accomplish 3-D structure, totally comprising one 100-nm-thick bottom-SiN/three 30-nm-thick sandwiched TEOS oxide/two 60-nm-thick sandwiched SiN/one 110-nm-thick top-SiN layers. After lithographic and anisotropic etching steps, a 3-level stacked dummy pattern was formed, followed by the formation of six nano-cavities underneath the sandwiched SiN layers by carefully-controlled lateral-etching of the TEOS oxide layers in a dilute HF solution as shown in Fig. 5-9 (a).

Here we performed anisotropic etching process in a transformer-coupled plasma (TCP) reactor using CF4 of 100 sccm, Ar of 50 sccm, and pressure set to 4.9 mtorr at RF power of 320 W for top electrode and 150 W for bottom electrode, to define 3-level multilayer-stacked dummy pattern. Figure 5-10 depicts the tilted SME images of anisotropic-etching dummy patterns, indicating that TCP reactor facilitates an abrupt etching profile. The overhead-view SEM images of the nano-cavities with 30- and 40-second lateral-etching time are depicted in Fig. 5-11, and both conditions exhibit obvious cavities between these sandwiched SiN layers. Afterwards, deposition of an in situ phosphorous-doped n⁺-poly-Si layer as NW channels and S/D regions (denoted as

3-level JL) was executed using SiH₄ of 0.49 slm and PH₃ of 15 sccm in a LPCVD system, followed by an anisotropic etching to define NW channels and S/D regions simultaneously, as illustrated in Fig. 5-9 (b). Note that control devices (denoted as 1-level JL) were also processed along with a similar flow, except the formation of 1-level stacked dummy pattern. To prevent the collapse of 3-level NWs, we retained portions of sandwiched SiN layers during the removal of 3-level stacked dummy patterns, instead of implementing GAA structure. Next, sequential depositions of gate dielectric stack comprising blocking oxide/trapping nitride/tunneling oxide (ONO) layers with thicknesses of 11/7/3 nm and 150-nm-thick n⁺-doped poly-Si films were executed to serve as gate dielectrics and electrode, respectively. Note that for the purpose of investigating the impacts of both enhanced current density and increased memory density with 3-D flash memories [27], we adopted the ONO gate dielectric stack rather than gate dielectric oxide layer. The cross-sectional TEM image of the fabricated 3-D stacked JL NW memory device is shown in Fig. 5-12, revealing that the 3-level stacked NWs with Ω-gate structure successfully avoid the occurrence of collapsed NWs after partially removing the sandwiched SiN layers of dummy patterns.

5.2-4 Planar Junctionless TFTs

Figure 5-13 briefly illustrates the key fabrication process flow of the proposed ultrathin JL poly-Si TFT. First of all, wet oxidation was performed to form 1000-nm-thick oxide on a six-in silicon substrate as the buried oxide [Fig. 5-13 (a)], followed by the deposition of a 17-nm-thick nitride layer as the etching-stop layer. A 9-nm-thick in situ phosphorous doped n⁺-poly-Si layer was deposited to serve as the channel layer [Fig. 5-13 (b)]. The poly-Si active region was then defined by lithographic and. subsequent anisotropic etching steps, followed by the successive depositions of a 13-nm TEOS oxide as the gate dielectric and 200-nm in situ n⁺-poly-Si as the gate electrode. Afterwards, the gate pattern was defined by a lithographic step and subsequently etched by reactive-ion etching, as shown in Fig. 5-13 (c). Sidewall spacers were formed with a 20-nm TEOS oxide layer and a 20-nm nitride layer [Fig. 5-13 (d)].

To reduce the parasitic S/D resistances, a 5-nm-thick nickel layer and a 15-nm-thick titanium nitride layer were first deposited [Fig. 5-13 (e)] and consecutively annealed to form NiSi on the gate, and S/D regions [Fig. 5-13 (f)], followed by a standard back-end process to form the metal connections. In contrast with JL devices, the control samples, denoted as inversion-mode (IM) counterparts, were fabricated with a similar process

flow. The major differences from the JL devices are the adoption of a 9-nm-thick undoped poly-Si channel and the S/D junctions formed with the implant-to-silicide technique [28]. Figure 5-14 displays the top-view SEM and cross-sectional TEM images of a fabricated JL device showing NiSi in the S/D regions. In the picture, an unexpected void above the NiSi region was formed during the preparation of the test sample by focus ion beam.

5.3 Measurement Setup

5.3-1 Electrical Measurement Setup

The experimental setup for the measurement of I-V characteristics consists of an HP4156A precision semiconductor parameter analyzer, an Agilent-81110A pulse generator, an Agilent-E5250A low leakage switch mainframe, and a Visual Engineering Environment (VEE) software. All the equipment is controlled by the interactive characterization software (ICS) program. An exsiccator and a temperature-regulated hot chuck are used to keep the humidity and temperature at the same level (relative humidity of 30% and 25 ^oC).

The HP-4156 provides a high current resolution to pico-ampere range for the current measurement. The Agilent-81110A with high timing resolution generates the pulse for transient and P/E characteristics. The Agilent-E5250A switches the signal from the HP-4156 and the Agilent-81110A to the device automatically. The measurement systems are applied to record the current-voltage (I-V) characteristics and test the memory characteristics.

5.3-2 S-Parameter Measurement Setup

To evaluate the high-frequency performances of fabricated JL poly-Si TFTs, S-parameters are measured on chip from 200 MHz to 20 GHz. The measurement system mainly consists of an Agilent N5245A PNA-X network analyzer, a bias-network (HP 11612V K11, HP 11612V K21), and a HP 4142B dc source/monitor, as illustrated in Fig.

5-15. All the equipment is controlled by the Agilent Integrated Circuit Characterization and Analysis Program (IC-CAP) software platform, and the data processing is served by IC-CAP as well. Afterwards, the measured S-parameters are used to acquire additional RF information such as cutoff frequency (f_t), maximum oscillation frequency (f_max), Y parameters and Z parameters, etc.

5.3-3 De-embedding Process

For the purpose of precisely measuring the high-frequency characteristics from devices, two-step correction procedure must be carried out. First step is to calibrate the whole measurement system. Available calibration techniques, including through-reflect-line (TRL), line-reflect-match (LRM), and short-open-load-through (SOLT), are commonly adopted to boost the accuracy of measurement results [29]. In the second step, the parasitic effects resulted from the bonding pads and interconnect have to be deducted owing to the significant coupling effects between the metals especially at high frequency. This is the so-called “de-embedding” procedure in terms of deducting the parasitic effects.

In our high-frequency characterization, we adopt the SOLT technique to calibrate the measurement system, and implement the aforementioned de-embedding procedure to remove the parasitic effects via open and short test fixtures. The SOLT calibration model consists of open-circuit capacitance, short-circuit inductance, matching load, and length of the through line [30]. Figure 5-16 illustrates the equivalent circuit diagram comprising the parallel parasitic capacitances (Yp1, Yp2, Yp3) and series parasitic impedances (Zp1, Zp2, Zp3) surrounding the transistor. The mask layout of open test fixture and the diagram of the equivalent circuit equipped with parallel parasitic capacitances are shown in Figs. 5-17 (a) and (b), respectively. The mask layout of short test fixture and the diagram of the equivalent circuit equipped with serial parasitic impedances and parallel parasitic capacitances are shown in Figs. 5-18 (a) and (b), respectively. In the first step of de-embedding process, the parallel parasitic capacitances and serial parasitic impedances can be separately calculated by mathematical matrixes described in Eqs. 5-1 and 5-2,

1 3 3

where Y_open is Y-parameter matrix measured from the open test fixture, and Y_short is Y-parameter matrix measured from the short test fixture. Next, the actual transistor’s Y-parameter matrix without parasitic effects can be calculated using Eq. 5-3:

1 1 1

( ) ( )

transistor DUT open short open

Y = Y −Y ⁻ − Y −Y ⁻ ⁻ ……….……...(5-3),

where Y_transistor is Y-parameter matrix measured from the transistor, and Y_DUT is Y-parameter matrix measured from the transistor with parasitic effects. By virtue of two-step de-embedding process, the impact of parasitic effects can be deducted and accordingly the accuracy of measured high-frequency characterization is guaranteed [31].

5.4 Results and Discussion

5.4-1 Electrical Characteristics of Junctionless NWFETs

Figure 5-19 shows the transfer characteristics of JL and IM devices with the TEOS oxide/TiN gate stack and its NW cross-sectional dimension as previously described in Fig. 5-4. The JL device with such tiny NW volume exhibits an on current-to-off current ratio (Ion/Ioff) ratio of 5.2 × 10⁶ at VG = 2 V and an excellent subthreshold slope (SS) of 199 mV/dec comparable to that in the IM counterpart (184 mV/dec). Owing to the adoption of the small volume of the NW channels together with GAA configuration, both IM and JL devices exhibit good transfer characteristics as expected [32]. But the on-state current drivability of IM device is obviously worse than that of the JL device.

The transconductance (Gm) versus gate voltage of the JL and IM devices with the TEOS oxide/TiN gate stack at V_D = 0.5 V is shown in Fig. 5-20. The Gm peak value of JL device is approximately five times larger than that of the IM one ascribed to the abundance of the carriers flowing through the body of the channel in the JL device.

Therefore, the I_on is inherently enhanced with the JL scheme. Figure 5-21 illustrates total resistance (R_total) versus channel length measured at V_G – V_th of 4 V and V_D of 0.15 V for both JL and IM devices with the TEOS oxide/TiN gate stack. The R_total can be calculated using the output characteristics data with various channel lengths and can be described as:

where R_SD is the S/D series resistance and R_ch is the channel resistance, respectively.

The R_SD could be estimated by extrapolating the curves to L = 0 since R_ch decreases to zero at L = 0, and accordingly R_SD could be extracted at low V_D and high V_G [33, 34].

The extracted R_SD are 0.49 and 9.65 kΩ for the JL and IM devices, respectively. The larger R_SD found in the IM device reveals that the JL technique can eliminate the S/D

junction-effect by its inherently homogeneous doping configuration from S/D to channel. On the other hand, the slope of the curves in the plot reveals the information of Rch per unit channel length, indicating that the IM device exhibits a larger Rch of 403.62 kΩ/μm, as compared with 108.66 kΩ/μm in JL one. Since the carrier transport in JL device is bulk conduction and accordingly the cross section for carrier flow is much larger than that in the IM counterpart. Consequently, both Rch and RSD are lower in the JL device, leading to the boosted current drivability as expected.

Figure 5-22 exhibits the transfer characteristics of JL and IM devices with the Al2O3/TiN gate stack and the correlative NW cross-sectional dimension as previously described in Fig. 5-5, while another two JL devices with larger channel cross sections are compared as well to evaluate the volume effect on the device switching-behavior.

Note that we denote JL and IM devices as doped channel (JL) and undoped channel (IM), respectively. Larger NW channels (Mid-sized JL and Large-sized JL) perform more aggravated switching properties in terms of poor Ion/Ioff behaviors. The conduction mechanism is through the current of majority carriers flowing in the bulk of the doped NW channel, and the bulk conduction path would be progressively depleted by decreasing the gate voltage to switch off the JL device, implying that the cross section of NW channel in the JL scheme has great impact on the device switching-behavior.

Note that we denote JL and IM devices as doped channel (JL) and undoped channel (IM), respectively. Larger NW channels (Mid-sized JL and Large-sized JL) perform more aggravated switching properties in terms of poor Ion/Ioff behaviors. The conduction mechanism is through the current of majority carriers flowing in the bulk of the doped NW channel, and the bulk conduction path would be progressively depleted by decreasing the gate voltage to switch off the JL device, implying that the cross section of NW channel in the JL scheme has great impact on the device switching-behavior.