Measurement Setup

4.3-1 Electrical Measurement Setup

Electrical measurements of all devices were performed by an HP4156A precision semiconductor parameter analyzer, an HP4284 LCR meter, an Agilent-E5250A switch, an Agilent-8110A pulse generator, and a temperature-regulated hot chuck. The hot chuck was used to maintain the measurement temperature at 25 ^oC. The measurement systems were applied to record the current-voltage (I-V) characteristics and test the hot-carrier reliability.

4.3-2 Hot-Carrier Stress Measurement Setup

In this study, we have executed the hot-carrier stress (HCS) to explore the impact of asymmetrical halo structure on device performance. The test samples with the channel width (W) of 10 μm and channel length (L) of 0.1 μm are chosen for the sake of small fluctuation in device characteristics as compared with L of 0.08 μm. In addition, devices for HCS were stressed with the drain voltage set at a highly positive voltage, and the gate terminal was biased at the voltage where maximum absolute value of substrate current (Isub) occurred to accelerate the degradation. To find the condition, we first measured the Isub-VG characteristics with drain terminal biased at moderate positive drain voltage. To monitor the hot-electron induced degradation, both the ID-VG

characteristics at V_DS = 50 mV (linear region) and charge pumping current were measured before and after the stress. The degradations in terms of threshold voltage shift (ΔVth), generation of interface trap density (ΔNit), transconductance degradation (ΔGm) and so on, were examined and recorded in the accelerated stress test.

4.3-3 Charge Pumping Measurement Setup

The charge pumping method, first proposed by Brugler and Jespers in 1969, is a powerful tool for interface trap measurements on small-geometry MOSFETs instead of large-diameter MOS capacitors [17]. In addition, this measurement allows the exclusion of gate leakage contribution to the calculated interface state densities existing within thin gate oxides and at lower frequencies [18-19], so we don’t need to pay attention to the leakage issue for precisely analyzing the interface state densities or the bulk traps in the gate dielectrics from the charge pumping measurement results. For better comprehension of the damage mechanism induced by HCS, it is important to profile the distributions of both generated interface states and trapped charges by the charge pumping method. The basic measurement is composed of applying a small fixed reverse bias to the S/D, connecting the substrate to ground, and performing a series of base voltage pulses with fixed amplitude, rise time, fall time, frequency, and duty cycle to the gate of the device from a low accumulation level to a high inversion level. The maximum charge pumping current will occur when the base level is lower than the flat-band voltage and the top level of the pulse is higher than the threshold voltage, revealing that once the device is pulsed from inversion toward accumulation, the net charges will be transferred from the S/D to the substrate through the fast interface traps and result in the charge pumping current. An MOSFET with a gate area of AG (=W×L) gives the charge pumping current (Icp) as [20]:

cp G it

I = ⋅ ⋅q f A ⋅N ……….…(4-4), while the interface trap density (N_it) could be calculated from this equation. On the contrary, the fast interface traps are continuously filled with electrons in the inversion level or holes in the accumulation level for nMOSFETs, while the base level of the pulse is higher than the threshold voltage or the top level is lower than the flat band voltage. It is impossible to generate the recombination current, and therefore no Icp can be collected.

There are three conventional types of voltage pulse train individually applying to the gate electrode, which are named as follows: (a) fixed peak sweep, (b) fixed base sweep, and (c) fixed amplitude sweep, as illustrated in Fig. 4-7. In this thesis, “fixed amplitude sweep” is used to calculate interface trap density, and “fixed base sweep”

mode is used to analyze the lateral distribution of interface trap, respectively. The basic setup of charge pumping measurement is shown in Fig. 4-8. Both source and drain are

biased at 50 mV while the substrate electrodes are connected to ground. Square-wave waveforms with 1 MHz provided by HP8110A are applied to the gate, and the base voltage is varied to transfer the surface condition from inversion to accumulation, while keeping the pulse amplitude at 1.5 V. In addition, the lateral distribution of generated interface states after the hot-carrier stress is extracted and discussed in this chapter. This scheme is developed by C. Chen et al. [21], and the measurement setup is shown in Fig.

4-9. The measurement procedures are described below:

(1) Measure the Icp-Vh curve (Vh is the high level of the pulsed voltage train applied to the gate as depicted in Fig. 4-9) on a virgin MOSFET from the drain junction (with the source junction floating), thereby establishing the Vh versus Vth(x) relationship near the junction of interest [22].

(2) Record the Icp-Vh characteristics after HCS.

(3) Get the hot-carrier-induced interface state distribution, Nit(x), from the difference of the Icp-Vh curves before and after HCS.

4.3-4 Flicker Noise Measurement Setup

Figure 4-10 illustrates the experimental setup for measuring low frequency flicker noise. The transistor is coupled to the pre-amplifier and noise analyzer. The output of the pre-amplifier is connected to the dynamic signal analyzer (DSA), executing both sampling and computing the Fast Fourier Transform of the input signal, and then calculates the density spectrum at the frequency of interest. A personal computer (PC) is used to control the correlative setups of measurement parameters, including the range of frequency and the voltage for four terminals (i.e., gate, drain, source, and bulk). Besides, an I-V meter is applied to measure the electrical characteristics and check if the test samples have failed during measurement. In this chapter, the frequency range of noise measurement is set from 10 Hz to 1 kHz.

4.4 Results and Discussion

4.4-1 Electrical Characteristics of TFETs

For all the measurements on the TFETs, we define the n⁺ region as drain and the p⁺ region as source. Dependence on different source dose splits of TFETs with W of 10 μm and L of 0.2 μm is shown in Fig. 4-11 biased at drain voltage (VD) of 0.5 V and source voltage (V_S) of -0.5 V, respectively. In this plot, none of them shows the emblematic

character of a TFET, i.e., a steep SS of sub-60 mV/dec, and the average SS of fabricated TFETs is beyond 300 mV/dec, indicating that even if the highest dose (1x10¹⁵ cm^-2) is adopted to increase the penetration probability of carriers, it still fails. This failure in steep SS would be ascribed to some potential culprits discussed as follows. Based on the work developed by Z. Qin et al. [23], SS can be reduced by increasing two components expressed as below:

while the tunnel-junction bias (Veff) governed by the gate-to-source voltage (VGS) is described as the first component in this equation, revealing that the implementation of both high-κ dielectric and ultra-thin body would be helpful. The second component describes that increasing the derivative of the junction electric field (ξ) on the VGS is effective to steepen SS. However, both the tunnel-junction bias (Veff) and ξ are coupled and cannot be engineered independently. Therefore, steepening SS is simpler to accomplish by the adoptions of high-κ dielectric and ultra-thin body. According to Eq.

4-5, both thick gate oxide of 2.5 nm and bulk silicon substrate of the fabricated TFET are the main culprits of flattening SS.

To demonstrate the functionality of p-i-n diode (source-channel-drain) in our fabricated TFET, we set the gate floating and applied voltage at the source side (p⁺ region) to comprehend the dependence of channel length on the channel conductance, as illustrated in Figs 4-12 and 4-13. Figure 4-12 shows the absolute value of source current versus source voltage curves with various channel length and W of 10 μm, indicating that all curves follow their good p-i-n diode behaviors. On the contrary, for those TFETs with the nominal channel length shorter than 100 nm, all the characteristics act like failed p-n diodes with incredible leakage currents as shown in Fig. 4-13, implying that the intrinsic portion of channel seems to disappear. Such phenomenon probably resulted from the thermal budget of dopant activation process, and hence the reliable channel length of fabricated TFETs is 200 nm as depicted in Fig. 4-12. The dependence of channel length on drain current is inherently different between TFETs and MOSFETs.

For the drain current behavior of TFET, Eq. 4-6 built by Krishna Kumar Bhuwalka et al.

[24] identifies the drain current of a TFET is independent of channel length.

1/ 2 3/ 2 concentrations and channel length (E_max=DV_GS, the maximum electric field across the tunnel junction). Figures 4-14 and 4-15 show the aforementioned channel-length dependence of nMOSFETs and TFETs, respectively. As can be seen in Fig. 4-14, drain current shows strong dependence on the channel length. On the contrary, the transfer characteristics of TFETs show indistinct IDS dependence on the channel length as illustrated in Fig. 4-15. Next, the impact of drain-to-source voltage (VDS) on the drain current is discussed with W/L = 10 μm/0.2 μm as shown in Fig. 4-16. In this plot, we set VDS at 1.25 V and modulate the drain voltage from -0.25 V to 0.75 V with step of 0.25 V.

From these different biased transfer curves, we find that they are not only parallel to one another but spaced out 0.25 V apart. The shifted transfer curves correspond with the same VD step of 0.25 V, agreeing with the work proposed by P.-F. Wang et al. [25]. In addition, the steepest SS among these biasing conditions occurring at VD of 0.25 V and VS of -1 V is 231 mV/dec, while the minimum value of average SS occurring at VD of

so we can see that SS is directly proportional to V_GS (strong dependence) and inversely proportional to Wg (weak dependence). Furthermore, the tunnel barrier width can be lowered with increasing VGS to improve the tunneling probability and drop SS [24].

Therefore precise control of S/D doping profile is extremely important for significant occurrence of BTBT, the doping concentration must be higher than 10¹⁹ cm^-3. Without abrupt S/D junction, the tunneling width would become long and worsen the SS. The doping concentration of boron in the source junction plotted by means of computer simulations for the fabricated TFETs is illustrated in Fig. 4-17. From this doping distribution plot, we clearly demonstrate our critical tunneling junction is not abrupt enough to BTBT, resulting in smooth SS beyond 300 mV/dec in average.

4.4-2 Electrical Characteristics of nMOSFETs

Figure 4-18 shows the transfer characteristics of all splits measured at VD=0.05 and 1.2 V with W/L = 10 μm/80 nm. Here we define the junction with halo as source in the Asy-Halo split for the forward mode operation, and thus the source of Asy-Halo split is biased with VD for the reverse mode operation denoted as Asy-Halo-R. As can be seen in the plot, the bulk punchthrough current becomes noticeable and leads to the horrible degradation of subthreshold characteristics in the Control split. Because the channel length is downscaling to some extent, even comparable to the depletion width of channel region, the sharing of the charges in the channel depletion region with the S/D junctions becomes noteworthy, and further, brings about the V_th lowering. As the gate length becomes shorter, the gate controllability becomes more impotent. On the contrary, the implementation of halo implantation in Sym-Halo split is helpful in keeping the subthreshold characteristics steep, and reducing the off-state leakage current (I_D at V_G = 0 V) by four orders of magnitude over the control, ascribed to both the improved subthreshold swing and the increased V_th. With the aid of halo implant, not only the depletion width of channel region can be reduced by increasing the substrate doping concentration locally, but also the lowering in surface potential barrier height with a high VD can be relieved. As far as the suppression of off-state leakage current is concerned, the Sym-Halo split is more efficient than the Asy-Halo split due to its inherently bilateral halo dopings, and therefore less penetration of drain-side electric field. Furthermore, the location of halo doping plays an important role in increasing the SCE immunity for the asymmetrical structures. As can be seen in the plot, the Asy-Halo-R split shows an improved DIBL as compared with the Asy-Halo counterpart, implying that the drain-side halo is more helpful than the source-side halo in suppressing the penetration of drain-side electric field into the channel region. Therefore, the halo doping is effective to restrain the SCEs even if unilateral structure is adopted.

The transconductance characteristics of all splits measured at VD=0.05 V with W/L = 10 μm/80 nm are plotted in Fig. 4-19. The output characteristics of all splits measured at V_G -V_th = 0~2 V in step of 0.4 V with W/L = 10 μm/80 nm are compared and shown in Fig. 4-20. Both transconductance and output characteristics of the Sym-Halo device are the worst among all splits and lower than the Control split by 19% (transconductance) and 25% (output current), respectively. This indicates that halo dopings would significantly degrade the device performance, which could be ascribed to the RSCE and

the degenerate carrier mobility induced by extra substrate doping in the channel. In fact, since the Asymmetric Halo split suffers from less degradation as compared with bilateral halo doping architecture (Sym-Halo), it shows a 7.8% higher transconductance and a 15% larger driving current. Even if the unilateral doping structure is adopted in the Asy-Halo-R split, there are 4.6% reduction of transconductance and 10% reduction of driving current as compared with the Asy-Halo counterpart. The differences of transconductance and driving current between the Asy-Halo and Asy-Halo-R splits result from the fact that the width of depletion region at drain junction is slightly thicker than that at source junction biased at a small VD, thus Vth of the Asy-Halo-R split is slightly higher than that of the Asy-Halo split, leading to the performance degradation.

Threshold voltage roll-off characteristics of all splits measured at VD = 0.05 V are shown in Fig. 4-21. The threshold voltage is defined as the gate voltage at drain current of (W/L) × 10 nA. The Sym-Halo split shows obvious RSCE among all splits because halo doping would increase the substrate doping concentration near the edge of the channel, and therefore causing the regional V_th rising. Besides, the V_th of Asy-Halo split is less than that of the Asy-Halo-R split with downscaling channel length due to their different depletion widths. In the case of Asy-Halo-R split, drain bias is applied at the drain junction with halo doping, and thus the width of depletion region at drain is thinner than that of the Asy-Halo counterpart. As a result, V_th of the Asy-Halo-R split is slightly higher than that of the Asy-Halo split. Figure 4-22 illustrates the drain-induced-barrier-lowering (DIBL) as a function of channel length for all splits to evaluate the short channel effect. We use the interpolation method to calculate DIBL effect. It is clearly seen that the devices with halo schemes depict better DIBL distribution, especially the bilateral halo structure. On the other hand, subthrehold swing (SS) is another criterion to evaluate the short channel effect. The SS as a function of channel length for all splits measured at VD = 0.05 V is plotted in Fig. 4-23. It can be seen that the Control split shows the worst SS degradation with decreasing channel. In addition, both Sym-Halo and Asy-Halo-R devices exhibit excellent robustness to SCE, implying that the drain-side halo undoubtedly increases the SCE immunity by effectively suppressing the penetration of drain-side electric field and reducing the drain-side depletion width. The Asy-Halo-R device has less penetration of electric field and smaller depletion width of the drain junction, and therefore, gives rise to the enhanced SCE immunity, including less Vth roll-off, better DIBL and steeper SS, as compared with the Control and Asy-Halo devices. However, you cannot sell the cow

and sup the milk. Halo implant also brings some side effects such as the drain-substrate coupling, the degradation of driving current and the enhanced RSCE. Figure 4-24 exhibits the on-state current (Ion) as a function of channel length for all splits to evaluate the penalty of halo implant. Ion is measured at VG -Vth = 1 V and VD = 1.2 V. The Sym-Halo device exhibits the worst Ion degradation among all splits, which is ascribed to the degenerate carrier mobility induced by extra substrate doping in the channel, while Asy-Halo and Asy-Halo-R splits show better current drivability due to their inherently unilateral halo structures. On the contrary, the Sym-Halo device shows the lowest off-state current (Ioff) as depicted in Fig. 4-25. The reduction of Ioff with halo scheme is ascribed to the Vth increment induced by RSCE. Figures 4-26 and 4-27 exhibit the transfer characteristics of 15 Control and 15 Sym-Halo nMOSFETs, respectively, with W/L = 10 μm/80 nm measured at VD = 1.5 V to leverage the degraded current drivability induced by the halo implant. As can be seen in these plots, the halo implant is beneficial to tightening the variation of device characteristics. Clearly the bilateral halo structure (Sym-Halo) can help reduce the device variation. Similar measurements were also performed on the unilateral-halo devices. The transfer characteristics of 15 Asy-Halo and 15 Asy-Halo-R nMOSFETs are shown in Figs. 4-28 and 4-29, respectively, with W/L = 10 μm/80 nm measured at VD = 1.5 V. The results clearly show that the Asy-Halo-R devices exhibit a tighter distribution of the current-voltage curves, confirming the ability of drain-side halo in preventing the penetration of electric field from the nearby junction into the channel.

4.4-3 Hot-Carrier Stress (HCS) of Asymmetrical Halo nMOSFETs

Next, we shift our attention to the hot-carrier characterization to discuss the impacts of bilateral or unilateral halo structures on the device reliability. The degradation induced by HCS in MOSFETs closely depends on the drain-side impact ionization under a high electric field horizontally [26-27]. The produced hot carriers are injected into the gate dielectric by hot-carrier injection, and thus lead to the interface states causing V_th shift, SS increment and performance degradation as time goes by [28].

In our case, these HCS-induced electrons and holes are collected by the drain and substrate terminals, respectively. Therefore, the substrate current (I_sub) can be used to monitor hot-carrier effect, and the impact ionization rate (Isub/ID) has been adopted to evaluate the amount of electron-hole pairs generated by impact ionization. Figure 4-30

shows the substrate current (I_sub) versus gate voltage for all splits of devices measured at V_Dof 3 V with W/L = 10 μm /100 nm. As can be seen in the plot, the devices with halo schemes exhibit larger Isub than the Control device, especially the Sym-Halo split.

Figure 4-31 depicts the impact ionization rate (Isub/ID) for all splits of devices measured at VD of 3 V with W/L = 10 μm /100 nm, and the adoption of halo architecture causes higher impact ionization rate (Isub/ID), while high Isub/ID is closely connected with the device with halo doping at drain side. In other words, the halo doping apparently has direct impact on the impact ionization process and the associated byproducts, hot electrons. In addition, both the largest Isub and Isub/ID of Sym-Halo split can be ascribed to the highest peak electric field under the gate edge of drain junction, consistent with the simulation results presented by T. N. Buti et al. [29-30] On the other hand, the Control and Asym-Halo devices exhibit lower Isub and Isub/ID than those devices with

Figure 4-31 depicts the impact ionization rate (Isub/ID) for all splits of devices measured at VD of 3 V with W/L = 10 μm /100 nm, and the adoption of halo architecture causes higher impact ionization rate (Isub/ID), while high Isub/ID is closely connected with the device with halo doping at drain side. In other words, the halo doping apparently has direct impact on the impact ionization process and the associated byproducts, hot electrons. In addition, both the largest Isub and Isub/ID of Sym-Halo split can be ascribed to the highest peak electric field under the gate edge of drain junction, consistent with the simulation results presented by T. N. Buti et al. [29-30] On the other hand, the Control and Asym-Halo devices exhibit lower Isub and Isub/ID than those devices with