Cg Gate capacitance
Ig Gate leakage current Id Drain leakage current
Ib Substrate leakage
EOT Effective oxide thickness
IL Interfacial layer
Nsub Substrate doping concentration Npoly Poly gate doping concentration
N(j,i) Hole density per unit area of the j-th subband in the i-th valence band Ninterface Interface trap density
Nt Trap density
Qdepl Depletion charge density tox Physical oxide thickness
tIL Physical IL thickness
tk Physical high- layer thickness tmix Physical thickness of transition layer
tbody Distance between two controlled gate stacks tstack Physical thickness of gate stacks (tk+tIL) xt Trap distance apart from IL/Si interface
xt_fav Specific favorable trap position can contribute maximum TAT current teff Effective thickness that the trap-assisted current flow mainly
W Channel width
Wmask Mask gate width
L Channel length
Fin Height Fin sidewall height of a FinFET a gate to STI spacing
Vthermal Thermal velocity (107 cm/s at room temperature)
Channel stress
c Trap cross section area
E(j,i) Energy of the j-th subband in the i-th valence band EVi Energy of the i-th valence band
EF Fermi level
Fs Silicon surface electric field strength Fk Electric field in high- layer
FIL Electric field in IL
F Fermi-Dirac distribution function
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mzhi Hole out-of-plane effective mass associated with the i-th valence band mdhi 2-D DOS (density of states) effective mass of the i-th valence band mox* Hole effective mass in oxide
mk* Tunneling effective mass in high- layer mIL* Tunneling effective mass in IL
m*k_h Hole tunneling effective mass in high- layer m*IL_h Hole tunneling effective mass in IL
m*M Effective mass in metal (1 m0)
f Impact frequency on the Si/SiO2(IL) interface Pt(E(j,i)) Hole transmission probability across the SiO2 film TWKB Transmission probability across the high- film TR Reflection correction factor
J Electron/hole direct/F-N tunneling current Jinterface Tunneling current from IL/Si interface states JTAT Trap-assisted-tunneling current JMGe Metal gate-to-substrate electron tunneling current
m Metal workfunction
k Band offset of high- layer with respect to silicon conduction band
IL Band offset of IL with respect to silicon conduction band
k_h Valence band offset of high- layer to silicon valence band
IL_h Valence band offset of IL to silicon valence band
k_e Conduction band offset of high- layer to silicon conduction band
IL_e Conduction band offset of IL to silicon conduction band
k_m (k_e + (m-s))
IL_m (IL_e + (m-s))
t Trap energy with respect to the valence band of high- layer or IL
depl(Vg) Potential band bending across depletion region versus gate voltage bias Window A local region, sited in the forbidden band gap with respect to conduction
(valence) band edge, allowing electrons (holes) to populate
Windowempty A region in IL/Si interface allows electron tunneling from metal-gate to occupy
si Silicon permittivity
ox Permittivity of SiO2
k Permittivity of high- layer
IL Permittivity of IL
mix(n) Permittivity of n-th abrupt barrier
k Electron affinity of high-k layer
IL Electron affinity of IL kB Boltzmann’s constant
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Chapter 1 Introduction
1.1 Background
Aggressive scaling of complementary metal-oxide-semiconductor field-effect transistors (CMOSFETs) continues for the purpose of reducing average cost per transistor, boosting device performance, and enhancing chip’s functionality with higher transistor density. Scaling of CMOSFETs is usually accompanied with equivalent oxide thickness (EOT) reduction for maintaining the gate control over the channel. However, the downward scaling of EOT directly increases the power consumption of the device because the leakage current increases significantly with decreasing physical thickness of gate dielectric. Advanced technologies are developed to overcome the leakage problem while keeping constant transistor performance improved. One of the crucial technologies is high- materials that are adopted in gate dielectric manufacturing [1.1],[1.2] with aim to reduce gate leakage. Due to thicker physical thickness of high- layer with the same EOT manufactured from conventional SiO2 dielectric, the leakage problem was mitigated. Furthermore, a tri-gate structure (FinFET) has attracted much attention in recent years [1.3]-[1.16].
Utilizing the strong gate control ability of tri-gate structure, the pressure on EOT scaling can be considerably released. Hence, the low gate leakage level can be hold as the scaling continues for FinFET structure.
Strain technologies are also extensively used to boost the transistor performance [1.17]-[1.20]. Due to serious power consumption issue originating from significant tunneling current in modern-day device, direct tunneling current across the gate oxide of MOSFETs has been extensively studied in the presence of an external
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mechanical stress applied during the measurement of this current [1.21]-[1.23].
Those studies attributed the external stress induced gate leakage change to both change of the carrier repopulation and the effective SiO2/Si barrier height due to strain induced band splitting. However, process-induced stress may affect some process parameters rather than simply the strain altered valence-band splitting. For example, the study has proven that oxidation rate can be affected by stressing [1.24].
The effects of process-induced variation on direct tunneling current have not been fully addressed. Hence, it remains unclear whether the trend of the hole direct tunneling with the external stress, as claimed in the literature [1.21],[1.22], could hold for the process induced case. In this work, the test samples are designed with different dimensions of gate edge to STI edge spacing in order to alter level of stress in channel. We find that the experimental hole gate direct tunneling current of p-MOSFETs versus STI (shallow trench isolation) induced longitudinal compressive stress, which does not appear to follow the trend [1.21],[1.22], is caused by the strain altered valence-band splitting alone. The physical explanation of the deviation between process- and external induced hole direct tunneling current change is systematically drawn. Furthermore, we find that direct tunneling current modeling can serve as a sensitive detector of process parameters.
The dimensions of CMOS continue to shrink such as to meet the requirements of Moore’s law that the number of transistors in a chip counts double every two years.
To keep the device performance improvement, the scaling procedure is not only to shorten the gate length but also scale the thickness of gate dielectric and depletion region in gate and substrate. One of most troublesome issues in scaling path is the unacceptable power consumption due to significant tunneling current effect as the oxide/oxynitride thickness is reduced down to around one nanometer. To solve this power consumption issue, high- materials were adopted in gate dielectric
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manufacturing [1.1],[1.2]. Comparing SiO2 gate dielectric counterpart, the high-
can achieve the same EOT but with thicker physical thickness of gate dielectric.
Therefore, the leakage current can be effectively reduced in MOSFETs with high-
gate dielectric. In addition, high- gate dielectric is usually integrated with metal gate in order to eliminate the poly depletion to get lower capacitance equivalent thickness (CET). Hence, metal-gate/high- gate stacks system has replaced poly-gate SiO2 gate dielectric system in advanced VLSI technologies. High- gate stacks usually include an ultra-thin interfacial layer (IL) for high quality Si-SiO2 interface beneath the high- material. Accurate modeling and characterization of the tunneling current through high- stacks is crucial to understanding the limitation in power consumption of the devices with high- metal-gate. Many studies [1.25]-[1.33] have been dedicated to modeling direct tunneling through high- gate stacks of MOSFETs.
However, these works, which neglected the transition of direct tunneling and Fowler-Nordheim (F-N) tunneling across high- layer [1.34], may lead to wrong fitting parameters. Because the band offset of high- materials to silicon is usually smaller than that of SiO2 [1.35], the transition between direct tunneling and F-N tunneling is potentially important in the modeling of tunneling current through high- gate stacks. In this work, combining the gate tunneling current fitting with its dlnI/dVg fitting, the gate tunneling current fitting guideline for accurately extracting the parameters of high- layer is created. The validity of this new proposed gate tunneling fitting guideline has been proven throughout this work, along with TaC/HfSiON/SiON and TiN/HfO2/SiON gate stacks n (p)-MOSFETs and metal-gate/HfO2 based high- layer/IL n-FinFET serving as test samples.
Furthermore, the gate leakage current modeling at low gate bias is still a challenge work. Hence, we propose a model for simulating electron tunneling from IL/Si interface states in forbidden band gap of Si to metal gate, with aim to explain the
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physical meaning of gate current at low gate bias. The validity of this extra modeling is verified experimentally throughout this work.
Following the fitting guideline established by electron tunneling current fitting of n-MOSFET with high- gate stacks [1.36], good reproduction of hole tunneling current is achieved and the corresponding material parameters are accurately extracted. However, based on our measured tunneling current data, we find that gate-to-substrate electron tunneling current (Ib) dominates overall gate leakage current at particular range of gate bias. This phenomenon is caused by the fact that tunneling barrier height seen by holes at inversion layer is higher than that seen by electrons in metal gate. Although Ib is getting importance for metal-gate high-
p-MOSFETs at inversion condition, its fitting work is still lacking. In this work, the hole tunneling current from both inversion layer and IL/Si interface states and gate-to-substrate electron tunneling at inversion condition in metal-gate high-
p-MOSFETs are excellently modeled.
As the scaling of CMOSFETs continues, maintaining the ability of gate control over channel is challenging. Short channel effect (SCE) and DIBL are serious issues in nano-scaled conventional planar devices. Under the circumstances, a transistor with 3-D multi-gate structure (FinFET) was developed [1.3]-[1.16]. The FinFET transistors have superior capability in gate control over planar transistors as the gate length becomes shorter and shorter [1.3],[1.7],[1.9]-[1.10]. Excellent short channel effect control was proven for gate length of less than 25 nm [1.9]-[1.10]. Owing to the strong ability of gate control, strict demand of EOT scaling is mitigated in FinFETs. In other words, the power consumption (due to gate tunneling leakage) issue in FinFET devices gets better control than that in planar ones. Although the FinFET structures were widely discussed in the open literature, the fitting work of gate tunneling leakage current in FinFET devices was rarely addressed [1.37]. In this
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work, with an analytical model for double-gate structure, reproduction of experimental gate tunneling current in metal-gate high- gate stacks nFinFET is achieved. The already established gate tunneling current fitting guideline for planar devices [1.36] has been successfully applied in fitting experimental gate tunneling current in metal-gate high- gate stacks FinFETs, leading to underlying process parameters.
1.2 Organization of this Dissertation
Introduction is given in Chapter 1. In Chapter 2, a strain quantum simulator is established. To control the process-induced channel stress, different gate edge to STI edge spacings are designed. Hole tunneling currents versus Vg for different STI-induced channel stresses are measured. Then, the physical origin of experimental hole current change due to process-induced stress is determined in terms of ultra-small oxide thickness change with internal stress.
Chapter 3 and 4 clearly describe direct and F-N tunneling models for metal-gate high- nMOSFETs. Reproduction of experimental tunneling current measured from TaC/HfSiON/SiON and TiN/HfO2/SiON gate stacks n-MOSFETs is achieved. A new advanced fitting approach by combining conventional Ig-Vg and Cg-Vg curve fittings with its dlnIg/dVg fitting is established. The ability and validity of this new gate tunneling approach are shown. Then, the fitting guideline of gate tunneling current for metal-gate high- nMOSFETs is established as well. Furthermore, the physical origin of experimental gate leakage at low gate bias is captured accordingly.
In Chapter 5, the theory and model of hole direct tunneling current for metal-gate high- pMOSFETs are presented. TaC/HfSiON/SiON and TiN/HfO2/SiON gate stacks pMOSFETs serve as test devices. Owing to the dominance of the gate-to-substrate tunneling current in overall gate current leakage, the model used for
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calculating metal-to-substrate electron tunneling current at inversion condition is constructed and discussed. Direct and F-N tunneling currents originating from hole inversion layer and IL/Si interface states are combined with TAT current component to explain experimental result.
Chapter 6 focuses on fitting gate tunneling current of FinFET transistors with metal-gate high- stacks. A simple simulator for double-gate structure is established and used to reproduce the tunneling current components through gate dielectric of FinFET. The validity of the simulator in combination of analytical tunneling model is confirmed for different fin widths. Good reproduction of electron gate leakage current versus Vg curve in a wide range of six decades is obtained.
Finally, in Chapter 7, the conclusions of the work are given and the major contributions are highlighted.
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