Comprehensive Modeling of Tunneling Current and its dlnI/dVg in High-k Metal-Gate p-MOSFETs
5.2 Physical Model
In this work, five tunneling mechanisms are used to explain the experimental data.
The clear descriptions of these tunneling models are presented below.
(i) Direct and F-N tunneling model for high-/IL gate stacks p-MOSFETs The energy band diagram of metal-gate/high-/IL/n-Si system in flat band condition is shown in Fig. 5.1. The material and tunneling related parameters in calculation are labeled as follows: m for metal-gate workfunction; k and IL for permittivity of high- layer and IL, respectively; tk and tIL for physical thickness of high- layer and IL, respectively; m*k_h and m*IL_h for hole tunneling effective mass in high- layer and IL, respectively; and k_h and IL_h for valence band offset of high- layer and IL to silicon valence band, respectively.
The analytical model of transmission probability (TWKB) through high-/IL stacks for n-MOSFETs is described in our previous work [5.13]. The same theory for TWKB
calculation can readily apply on metal-gate high- p-MOSFETs. Three tunneling cases are included in calculation and the corresponding band diagrams are depicted in
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Fig. 5.2. The analytical formula of TWKB for three tunneling cases can read as follows:
Tunneling case I ((j1(E) > 0, j2(E) > 0, j3(E) > 0, j4(E) > 0)): direct tunneling through both high- layer and IL. TWKB is the product of direct tunneling probability for both layers as follows:
3/ 2 3/ 2 3/ 2 3/ 2 through the IL and F-N tunneling occurring in high- layer. TWKB is the product of direct tunneling probability for IL and F-N tunneling probability for high- layer as follows: through the IL. TWKB is direct tunneling probability through IL as follows:
3/ 2 3/ 2
where j1 and j2 are tunneling barrier height seen by holes at subband j, vally i for high- valence-band sidewall edges; j3 and j4 are tunneling barrier heights seen by holes at subband j, vally i for IL valence-band sidewall edges; and Fk and FIL are the electric fields in the high- layer and IL, respectively.
Then, the hole tunneling current can be calculated:
2
where f is the hole impact frequency at the interface of IL/Si; g2D is the 2-dimensional density-of-states per unit area; F is the Fermi-Dirac distribution; TR is the reflection correction factor at the interface of IL/silicon. The reflection at the interface of
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high-/IL and metal gate/high- is weak and thus is neglected in the calculation.
(ii) Trap-assisted tunneling (TAT) for high-k/IL gate stacks p-MOSFETs
Trap-assisted tunneling model was used to explain the stress-induced leakage current (SILC) for SiO2/SiON gate dielectric MOSFETs [5.14]-[ 5.16], as well as the gate leakage current in metal-gate/high- MOSFETs [5.17]. Energy band diagram of the metal gate/high-/IL/n-Si system for description of the TAT mechanism is shown in Fig. 5.3. The trap-assisted tunneling current can be calculated [5.15]:
_ _
if a hypothetical trap is in IL, the TWKB_in/out can be modified as:
3/ 2 3/ 2
if a hypothetical trap is in high- layer, the TWKB_in/out can be modified as:
3/ 2 3/ 2
where Jin_trap and Jout_trap are the tunneling current density from inversion layer to trap state and the tunneling current density from trap state to gate, respectively; t is trap energy with respect to the valence band of high- layer or IL; tstack is the physical
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thickness of gate stacks (tk+tIL); Nt is the trap density; and xt is the trap distance apart from IL/Si interface.
As the trap located at specific favorable trap position (xt_fav) can contribute maximum TAT current, the equation (5.5) can be approximated as:
_ ( _ ) _ ( _ ) where teff is the effective thickness that the trap-assisted current flow mainly [5.15];
and c is the trap cross section area . The value of teff is estimated at 0.33 nm and that is independent of gate voltage bias, as reported in [5.15].
(iii) Metal gate-to-substrate electron tunneling current for high-k/IL gate stacks p-MOSFETs
The band diagram of metal/high-/IL/n-Si system at inversion condition for description of the gate-to-substrate electron tunneling mechanism is shown in Fig.
5.4(a). The band diagram of metal-gate/high-/IL/n-Si system at flat band condition with the labels serving as input parameters is shown in Fig. 5.4 (b). In the figure, k_e
and IL_e are the conduction band offset of high- layer and IL to silicon conduction band, respectively; k_m and IL_m are defined as (k_e + (m-s)) and (IL_e + (m-s)), respectively; m*k_e and m*IL_e are the electron tunneling mass in high-
layer and IL, respectively; and a region in IL/Si interface called Windowempty allows electron tunneling from metal-gate to occupy. Note that k_e can be determined by means of electron tunneling current and its dlnI/dVg fittings at inversion condition for n-MOSFETs.
Based on the study reported by Yang et al. [5.18], the gate-to-substrate tunneling current for high-k metal gate p-MOSFETs can be modified as:
* max
86 electron energy in metal gate reference to the bottom edge of Windowempty and only the electrons in gate with the energy of EM>0 have the opportunity to tunnel from gate to substrate.
(iv) Hole tunneling from IL/Si interface states to metal-gate
In Fig. 5.5, the meaning of “Window” is a local energy region with respect to valence band edge in the forbidden band gap, allowing holes to populate. A simple model for calculating the hole current tunneling from IL/Si interface states (Jinterface) can read as:
interface thermal interface
( )
WKB( )
J qV N F E T E dE
(5.14) where Vthermal is thermal velocity (107 cm/s at room temperature); and Ninterface is interface trap density in “Window” (cm-3eV-1) and is used as fitting factor in this work.With combinations of these tunneling models, the experimental tunneling currents measured from source/drain, gate, and bulk terminals at strong inversion condition for metal-gate high- p-MOSFETs can be reproduced well. The details and fitting results are shown later.