Physical Origin and Discussion

To find out the plausible physical mechanisms that account for the hole gate current enhancement, we employed the above verified quantum strain simulator through the changes in the process parameters. First, with polysilicon doping concentration Npoly and substrate doping concentration Nsub both fixed at their nominal values, the simulated gate current change percentage is givenin Fig. 2.9(a) versus gate voltage with the gate oxide thickness tox as a parameter. The corresponding fractional gate current change, remains constant in a wide range of the gate voltage, regardless of tox. This means that the same flat characteristics as those experimentally encountered over the gate voltage can be reached as long as the appropriate gate oxide thickness has been determined. Secondly, to reflect the stress effect on impurity diffusion [2.9],[2.11]-[2.13], additional simulations were conducted for varying Npoly

and Nsub. The results are given in Fig. 2.9(b) and 2.9(c). The gate current change

13

presented in Fig. 2.9(b) corresponds to two different values of Npoly under fixed tox and Nsub, clearly revealing a profoundly significant deviation for more negatively biased gate voltages. Such a huge deviation also appears in Fig. 2.9(c) for two different values of Nsub under fixed tox and Npoly, which occurs instead in the direction of less negative gate voltage. Therefore, the stress induced dopant redistribution is unlikely to serve as the responsible mechanism. Furthermore, the remaining possible factors were considerably ruled out: (i) the channel area change due to source/drain extension diffusion retardation [2.9],[2.13] is insignificant (10^-3); and (ii) the trap assisted tunneling as the dominant mechanism is impossible because of less correlation with the mobility data in Fig. 2.2; specifically, the mobility change at -215 MPa stress is about three times the gate current change.

The above analyses suggest the reduction in the physical gate oxide thickness over the whole gate area, as the principal factor in producing the gate current enhancement. Thus, the quantum strain simulation was further carried out for different gate oxide thicknesses with other process parameters kept unchanged. The results are plotted in Fig. 2.10 versus stress along with the data for comparison. The underlying gate oxide thickness can be straightforwardly obtained with an accuracy of 0.001 nm:

tox = 1.267 and 1.264 nm for -120 and -215 MPa stress, respectively. The extracted gate oxide thickness reduction is around 0.003 and 0.006 nm for -120 and -215 MPa stress, respectively. Again, the gate current change for tox = 1.264 nm and  = -215 MPa was simulated with respect to the nominal case (tox = 1.27 nm and  = 0 MPa).

The results are given in Fig. 2.5. Here it can be seen that good agreements with the data are created for a wide range of gate voltage down to -0.2 V, achieved without adjusting any parameters.

At this point, it is interesting to make a comparison with the existing thermal oxidation experiment on a bending silicon wafer [2.14],[2.15]. In one of the citations

14

[2.14], an externally applied mechanical stress of -100 MPa was shown to have no noticeable effect on the thickness of the formed oxide (800 ^oC dry O2 100%

oxidation), especially in a certain range down to 2 nm thick which is comparable with the gate oxide thickness used in this work. In the second citation [2.15], the effect of the external compressive mechanical stress was also shown to be insignificant as well, valid with an accuracy of 0.5 nm. However, with the combination of both the quantum strain simulator and the hole direct tunneling data as done in this work, we reached the gate oxide thickness with the greatly improved precision down to 0.001 nm.

Indeed, it is difficult for current capacitance measurements to deliver such a precision of 0.001nm or 0.08% in gate oxide thickness variation. However, direct tunneling current itself is highly sensitive to the change in the gate oxide thickness. This means that the gate direct tunneling current may serve as an ultra-precision detector of the oxide thickness. However, care must be taken in this direction. This explains the importance of a quantum simulator as demonstrated in this work.

Additionally, the inset of Fig. 2.4 clearly points out that the standard deviation of the gate current is comparable between different gate-to-STI spacing values. This dictates that the spatial fluctuation in the gate oxide thickness is caused by the random process during the thermal oxidation, regardless of the stress. Only the average of the gate current steadily increases with the stress. This means that applying a compressive stress may retard the oxidation rate and thus give rise to a reduction in the physical gate oxide thickness. On the other hand, the presented change of up to 0.47 % in the gate oxide thickness is larger than that (0.03 %) caused by the Poisson’s ratio [2.1].

This means that the strain-retarded gate oxidation rate may dominate over the strain altered valence-band splitting counterpart. As a result, the currently recognized trend [2.1],[2.2] that the hole gate direct tunneling current decreases with the compressive stress is significantly reversed, as clearly demonstrated in this work.

15

Finally, the simulator was again carried out to examine the effect of the poly stress. The resulting gate current change of zero poly stress with respect to poly stress of -215 MPa is plotted in Fig. 2.11 as a function of gate voltage for channel stress of -215 MPa. It can be seen from the figure that significant discrepancies exist, especially for less negative gate voltage. Thus, this deviation, as well as its striking trend, can provide the extra evidence to support the aforementioned hypothesis that the poly stress is close to the channel stress. On the other hand, modeling the gate current through a metal-gate/high-k/interfacial SiO2/p-type inversion layer/n-type silicon system remains to be a challenging issue. It is expected for the presented simulator to find applications in this metal-gate high-k gate stack case. To achieve the goal, some suggestions are given. First of all, the subband energy calculation by the triangular potential approximation in the presence of the stress can be directly applied in the p-type inversion layer. The corresponding energy band diagram in Fig. 2.6 can be retained but with the poly side removed. The remaining energy band part corresponding to the metal gate and high-k dielectrics may be roughly constructed from the electrostatics aspects in terms of the capacitance, the inversion charge density, and the threshold voltage. Refining of the overall band diagram may be achieved through the fitting of the gate current. At this point, the tunneling model used in this work must be modified substantially. Specifically, the trap-related tunneling might dominate the overall gate current in metal gate/high-k devices due to the thicker insulator and the higher trap density within the insulator of the metal gate/high-k devices. Multilayer tunneling and/or hopping mechanisms may be significant as well.

2.5 Conclusion

The measured hole gate direct tunneling current on a nominal 1.27-nm gate

16

oxide p-MOSFET has exhibited an increasing trend with STI compressive stress, exactly contrary to that of the externally applied compressive stress. To resolve this contradicting issue, a quantum strain simulator has been established. The validity of the simulator has been examined in detail. The combination of the verified simulator and the experimental data has systematically led to the finding of the origin: A reduction in the apparent physical gate oxide thickness over the whole gate area, with an accuracy of 0.001 nm, occurs under the influence of the STI compressive stress. A linkage to the mechanical stress dependent thermal oxidation experiment in the open literature has been constructed. The extracted gate oxide reduction in this work has been shown to be able to significantly enhance the hole direct tunneling current and consequently reverse the conventional trend with the stress. Some suggestions have also been given concerning the application of the simulator in the metal-gate/high-k devices.

17

Fig. 2.1(a) Schematic demonstration of the cross-sectional view of the test device.

Fig. 2.1(b) Schematic demonstration of topside view of the test device. The gate edge to STI edge spacing as labeled a is highlighted. The compressive stress is due to the lower thermal expansion rate of STI oxide compared to silicon.

18

0 -50 -100 -150 -200 -250 -4

0 4 8 12 16 20

0 2 4 6 8 10

0.0 0.2 0.4 0.6 0.8 1.0

Gate-to-STI Spacing a (m)



(a)/

(a

)



/ 

(%)