• 沒有找到結果。

Electron Tunneling Current

7.2 Suggestions to Future Work

One of the main contributions in this dissertation is that a curve fitting around the peak of dlnIg/dVg-Vg can help accurately determine the band offset of high- layer to silicon conduction band. If we further observe the temperature dependence of the dlnIg/dVg-Vg curve, some new insight into the band offset of high- layer may be obtained.

In this work, several remarkable findings about the properties of high- gate stacks have been presented. First, interface states dominant gate leakage current at low gate bias has been demonstrated. Second, the HfO2 based high- layer may have transition layer between high- layer and IL but HfSiON may not have that. However, how the transition layer and interface states affect mobility properties is an important topic. It is interesting to observe if theoretically calculated mobility with those Ninterface

obtained by gate current fittings can match the experimental mobility at low Vg. This approach can further verify the value of Ninterface. By manufacturing two different high- gate stacks: one has transition layer but the other does not have, the effect of transition layer on mobility can be captured. Furthermore, the kinetic tapping and de-trapping properties of the trap states in the presence of a gradual transition layer between high- layer and IL may be examined by means of RTS and low-frequency noise measurement. Finally, many studies show a strong relationship of NBTI with interface traps. Hence, a further task to relate the measured gate leakage current at low gate bias to NBTI stress is worthy to do.

151

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Chapter 2

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IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 1010-1020, May 2006.

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[2.13] Y. M. Sheu, S. J. Yang, C. C. Wang, C. S. Chang, L. P. Huang, T. Y. Huang, M. J. Chen, and C. H. Diaz, “Modeling mechanical stress effect on dopant diffusion in scaled MOSFETs,” IEEE Trans. Electron Devices, vol. 52, no. 1, pp. 30-38, Jan. 2005.

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Chapter 3

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Ghani, R. Grover, W. Han, D. Hanken, M. Hattendorf, J. He, J. Hicks, R.

Huessner, D. Ingerly, P. Jain, R. James, L. Jong, S. Joshi, C. Kenyon, K.

Kuhn, K. Lee, H. Liu, J. Maiz, B. McIntyre, P. Moon, J. Neirynck, S. Pae, C.

Parker, D. Parsons, C. Prasad, L. Pipes, M. Prince, P. Ranade, T. Reynolds, J.

Sandford, L. Shifren, J. Sebastian, J. Seiple, D. Simon, S. Sivakumar, P.

Smith, C. Thomas, T. Troeger, P. Vandervoorn, S. Williams, and K.

Zawadzki, “A 45 nm logic technology with high–k+ metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100%

Pb–free packaging,” in IEDM Tech. Dig., Dec. 2007, pp. 247–250.

[3.2] S. Natarajan, M. Armstrong, M. Bost, R. Brain, M. Brazier, C.–H. Chang, V.

Chikarmane, M. Childs, H. Deshpande, K. Dev, G. Ding, T. Ghani, O.

Golonzka, W. Han, J. He, R. Heussner, R. James, I. Jin, C. Kenyon, S.

161

Klopcic, S.–H. Lee, M. Liu, S. Lodha, B. McFadden, A. Murthy, L. Neiberg, J. Neirynck, P. Packan, S. Pae, C. Parker, C. Pelto, L. Pipes, J. Sebastian, J.

Seiple, B. Sell, S. Sivakumar, B. Song, K. Tone, T. Troeger, C. Weber, M.

Yang, A. Yeoh, and K. Zhang, “A 32 nm logic technology featuring 2nd–generation high–k+ metal–gate transistors, enhanced channel strain and 0.171 μm2 SRAM cell size in a 291 Mb array,” in IEDM Tech. Dig., Dec.

2008, pp. 941–943.

[3.3] M. Depas, B. Vermeire, P. W. Mertens, R. L. Van Meirhaeghe, and M. M.

Heyns, “Determination of tunneling parameters in ultra-thin oxide layer poly-Si/SiO2/Si structures,” Solid-State Electronics, vol. 38, no. 8, pp.

1465-1471, Aug. 1995.

[3.4] B. Brar, G. D. Wilk, and A. C. Seabaugh, “Direct extraction of the electron tunneling effective mass in ultrathin SiO2,” Appl. Phys. Lett. vol. 69, no. 18, pp. 2728-2730, Oct. 1996.

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Chapter 4

[4.1] S. Zafar, C. Cabral, R. Amos, and A. Callegari, “A method for measuring barrier heights, metal work functions and fixed charge densities in

[4.1] S. Zafar, C. Cabral, R. Amos, and A. Callegari, “A method for measuring barrier heights, metal work functions and fixed charge densities in

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