Test Samples

Two presented samples were p-MOSFETs with TaC/HfSiON/SiON and TiN/HfO2/SiON gate stacks. The material and process parameters for these test devices can be determined by the extraction approach addressed in our previous work [5.13]. One of the test devices is p-channel MOSFET with TiN/HfSiON/SiON gate

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stack fabricated in a state-of-the-art process [5.19]. Nominal physical thicknesses of HfSiON (tk) and SiON (tIL) were 2.2 and 1.3 nm, respectively. Through Cg-Vg fitting, as shown in Fig. 5.6(a), we obtained EOT of 1.5 nm, metal-gate work function m of 4.48 eV, and n-type substrate doping concentration of 1μ10¹⁷ cm^-3. The permittivity of HfSiON (k) was estimated at 12.4 0 [5.19]. To meet EOT = 1.5 nm, the permittivity of SiON (IL) was determined to be 6.2 0 and hence the conduction (valence) band offset of SiON to silicon conduction (valence) band edge was IL_e = 2.54 (IL_h = 3.06) eV [5.20].

Using the same extraction approach, the parameters of TiN/HfO2/SiON gate stacks p-MOSFETs can further be determined. The corresponding Cg-Vg fitting is shown in Fig. 5.6(b). The parameters for TiN/HfO2/SiON gate stacks p-MOSFETs are: EOT = 0.85 nm, m = 4.5 eV, Nsub = 6μ10¹⁷ cm^-3, tk = 1.4 nm, and tIL = 0.9 nm. The permittivity of HfO2 was estimated at 22 0 [5.21]. To meet EOT = 0.85 nm, the permittivity of IL was estimated at 5.8 0 and its corresponding IL_e (IL_h) was estimated at 2.623 (3.35) eV [5.20]. The effects of the uncertainties in the values of IL

and IL, as well as tIL and tk, on fitting results can be neglected, as have been demonstrated in our previous work [5.13].

5.4 Experimental and Fitting (i) TaC/HfSiON/SiON p-MOSFETs

The tunneling current was measured from TaC/HfSiON/SiON p-MOSFETs with the source, the drain, and the substrate tied to the ground. The measured results are shown in terms of the solid symbols in Fig. 5.7. The current detected from drain terminal (Id) is the hole tunneling current and the current detected from substrate terminal (Ib) is the gate-to-substrate electron tunneling current. The gate current is the total tunneling current through the gate stacks. We find that the Ib current dominates

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the overall gate current at some range of gate voltage biases. Two reasons can explain this. First, the tunneling barrier height of high- layer and IL for hole tunneling is usually higher than that for electron tunneling. Second, the Fermi level of metal-gate usually aligns with the mid-gap of silicon. Thus, the tunneling barrier height seen by electrons in metal gate is much lower than that seen by electrons in p⁺-poly gate at strong inversion condition.

Based on the tunneling model described in the section of physical model, the good fittings of Id and its dlnId/dVg versus Vg curves at strong inversion condition are done, as shown in Fig. 5.8. The fitting parameters used for the red fitting line in Fig.

5.8 are k_h = 3 eV, mk_h* = 0.03 m0, and mIL_h* = 0.67 m0. Additionally, gate-to-substrate (Ib) tunneling current modeling was performed as well. With the variable Windowempty introduced in Fig. 5.4(a), good fitting of Ib is obtained as shown in Fig. 5.9. This result suggests that there are many interface traps, close to conduction band in the Si forbidden gap, having strong ability to allow electron tunneling from metal-gate to occupy. This conclusion about interface traps is self- consistent with the results of Jinterface dominating the gate leakage at low gate bias for metal-gate high- nMOSFETs in previous chapters. The fitting parameters used for best Ib fitting are k_m = k_e+(m-s) = 1.1+(4.48-4.05) eV, m*k_e = 0.03 m0, m*IL_e = 0.95 m0, and Windowempty = 0.1 eV. The parameters used for electron tunneling calculation such as k_e, mk_e*, and mIL_e* are based on the values extracted in our previous work for n-MOSFETs with the same gate stacks [5.13]. Other parameters extracted by Cg-Vg fitting hold unchanged for both Idand Ib fittings.

In contrast to our previous work [5.13], no peak is observed in dlnId/dVg-Vg curve due to large valence band offset of HfSiON to silicon valence band. We find at least two sets of parameters that can be used to fit the experimental Id well, as shown in Fig.

5.8. Hence, without the information obtained from a transition between direct and F-N

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tunneling in current fitting, the parameters like k_e/h and m*k_e/h cannot be determined.

It suggests that the studies [5.3]-[5.12] to extract the parameters such as k_e/h and m*k_e/h dealt with only a curve fitting of tunneling current data, which may lead to wrong values of extracted parameters.

We still try to explain the mismatch between experiment Id data and simulated hole tunneling current at low gate bias. The schematic band diagram for description of the mechanism of Jinterface is shown in Fig. 5.5. The excellent refitting work of experiment (Id) with additional Jinterface calculated by equation (5.14) was obtained, as shown in Fig. 5.10. Based on the good fitting result, the leakage current at low gate bias is ascribed to Jinterface. Finally, the total current though the gate stack (Ig) is estimated in terms of the summation of calculated Id and Ib. The good fitting results are shown as open symbols in Fig. 5.7.

(ii) TiN/HfO2/SiON p-MOSFETs

Current separation measurement was performed for TiN/HfO2/SiON gate stacks p-MOSFETs, as shown in Fig. 5.11. First, we use direct and F-N tunneling current model to fit the experimental hole tunneling current (Id), as shown as black line in Fig.

5.12. However, simulated hole gate current has much stronger Vg dependence than that of experimental data. This suggests that other mechanisms dominate the experimental Id current. In this work, TAT mechanism is used to explain weak Vg dependence in the experiment. With the favorable trap position estimated at 0.6 nm away from interface of IL/Si by means of the calculated tunneling probability versus trap position curve shown in Fig. 5.13, TAT current can be calculated by a simplified equation (5.11). The calculated TAT current result with xt_fav = 0.6 nm, t = 3.35 eV, and teffμcμNt = 3.3μ10^-3 presents good reproduction of Id at -2.5< Vg < -1 V, as shown as red line in Fig. 5.12. In the figure, t is assumed to be equal to IL_h due to its weak effect on TAT current for ultra-thin gate stack; and teffμcμNt = 3.3μ10^-3 is a

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fitting parameter and this value is comparable with another group＇s result (1μ10^-3) in the open literature [5.15]. Combining calculated direct and F-N tunneling current with TAT current, the experimental Id for TiN/HfO2/SiON gate stacks p-MOSFET can be fitted very well at strong inversion condition, as shown as blue line in Fig. 5.12(a).

The corresponding dlnId/dVg is also fitted well, as shown in Fig. 5.12(b). The k_h = 1.95 eV and m*k_h = 0.08 m0 can be determined accurately by means of the peak horizontal position and peak height of dlnId/dVg-Vg curve, respectively. The ability of dlnI/dVg fitting for accurately extracting the parameters of high- layer still works in p-MOSFETs.

The importance of dlnId/dVg-Vg fitting is highlighted in Fig. 5.14. Without considering the dlnId/dVg fitting, a fair good fitting of experiment data is presented with a large test value of k_h = 3 eV for the purpose to vanish the F-N tunneling mechanism at a gate bias range of |Vg|<3V, as shown in Fig. 5.14(a). However, the simulated of dlnId/dVg-Vg curves significantly deviate from the experimental data, as shown in Fig. 5.14(b). Hence, for getting the accurately parameters of high- layer, extra dlnId/dVg fitting is needed. Additionally, comparing the simulated results in Fig.

5.12 (b) with that in Fig. 5.14(b), we can further confirm that the peak in experimental dlnId/dVg-Vg curve is caused by a transition between direct and F-N tunneling rather than caused by a transition between direct tunneling and TAT.

The gate-to-substrate electron tunneling current fitting for TiN/HfO2/SiON p-MOSFETs is performed with two different values of Windowempty, as shown in Fig.

5.15. Again, with non-zero value of Windowempty, good reproduction of Ib for TiN/HfO2/SiON gate stacks p-MOSFETs is obtained. The best fitting parameters are:

k_m = 1+(4.5-4.05) eV, m*k_e = 0.03 m0, m*IL_e = 0.85 m0, and Windowempty = 0.15eV.

Jinterface is used to explain the hole gate leakage (Id) at a low gate bias range that still

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cannot be explained by TAT. A complicated and huge work was done, as shown in Fig.

5.16. Combining calculated DT, F-N, and TAT current from inversion layer with Jinterface, an excellent reproduction of complicated experimental Id curve in a wide current range of eight decades is achieved. Both the very large fitting value of Ninterface

(1.1μ10²² cm^-3eV^-1) and the occurrence of TAT mechanism suggest that the quality of high- gate stacks near Si valence band edge is terribly poor. There may be some relation between the large Ninterface and occurrence of TAT. Finally, combining the simulated results of Id and Ib, the good fitting of experimental Ig is shown in Fig. 5.11.

The complete tunneling fittings for TaC/HfSiON/SiON and TiN/HfO2/SiON gate stacks p-MOSFETs are demonstrated in this work.

In this work, we neglect the effects of the transition layer on tunneling current calculation because the transition layer only affects the gate current at a gate voltage bias behind the F-N tunneling occurrence, as shown in Fig. 5.17. Due to the large band offset of high- layer to Si valence band edge for our test samples, the transition layer effect on gate current fitting may be numerically neglected.

5.5 Conclusion

The gate-to-substrate electron tunneling current and hole tunneling current from inversion layer and IL/Si interface states for TaC/HfSiON/SiON and TiN/HfO2/SiON gate stacks p-MOSFETs are reasonably modeled. The corresponding tunneling physical models are clearly described as well. Combining TAT with Jinterface models can explain the small Vg dependence of experimental hole tunneling current for fresh TiN/HfO2/SiON stacks p-MOSFETS. By means of advanced fitting work, Jinterface is determined to be responsible for experimental hole leakage current at low gate bias for the test devices. The importance of substrate tunneling current in overall gate leakage current for metal gate high- p-MOSFETs is highlighted. Finally, with the

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additional of dlnI/dVg fitting, we find that the valence band offset of HfSiON to silicon is larger than that of HfO2.

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Fig. 5.1 Schematic of the energy band diagram of a metal-gate/high-/IL/n-Si system biased in flat-band condition. The process and material parameters for hole tunneling current calculation are labeled.