Motive of the Thesis

Increased short-channel effects (SCEs) appear as a major obstacle to preserve the performance enhancement in conventional bulk Si MOSFETs with sub-micron technology node. According to International Technology Roadmap for Semiconductors (ITRS) [1], incorporation of new technologies is becoming crucial for deep sub-micron CMOS devices. It is reported that the non-planar MOSFETs of double-gate, triple-gate, and surrounding-gate MOSFETs are attractive devices for the extremely small device scaling. These devices offer a higher current drive per unit silicon area than conventional MOSFETs. Although these non-planar devices are superior over conventional planar devices in respect of suppressing the short-channel effects (SCEs), the formation of ultra-sharp and super-shallow source/drain junctions to suppress SCEs still stringently constrain the doping techniques and thermal budget. Recently, a new kind of device named junctionless (JL) transistor has been proposed to alleviate these challenges [2]. The absence of doping concentration of junctionless transistor gradient between source/drain and channel eliminates the problem of sharp doping profile formation and saves the thermal budget. However, the generic mechanism of the hot-carrier-induced trapped charges was revealed in the previous literature [3]. It indicates that the device/circuits degradation with the trapped charges is mainly caused by accumulated dc stress under the condition that the gate voltage is near the threshold voltage and the high drain voltage, i.e., the drain-avalanche hot-carrier (DAHC) stress condition. In other words, the damaged zone and the interface positive/negative trapped charges can be attributed to DAHC. Several studies have modeled the

hot-carrier-induced threshold voltage of the planar and the double-gate MOSFETs in the past decade [4] [5]. However, there is little paper to investigate the threshold voltage model of surrounding-gate MOSFETs with the interface trapped charges. To overcome limitations and realize high-performance MOSFETs, by considering effects of equivalent oxide charges on the flat-band voltage, effective conducting path, and Poisson’s equation, a concise analytical subthreshold behavior model for JL\JB MOSFETs with the interface trapped charges including threshold voltage, subthreshold slope, and subthreshold current are needed.

Among different possible solutions, non-conventional MOSFET device structure employing the gate material engineering [6] improves the gate transport efficiency by modifying the electric field pattern and the potential along the channel, resulting in higher carrier transport efficiency and SCEs suppression. During the last decade, high-k dielectrics have been studied as an alternative to SiO2 based gate dielectric to reduce the gate leakage current. The use of high-k materials in the oxide region can effectively reduce gate leakage current with continuous thinning of gate oxide layer [7]. The gate-stack structure with a gate oxide of SiO2 as an interfacial buffer between bulk silicon and high-k dielectrics can screen the effect of phonon scattering and improve the carrier mobility [8]. The straddle-gate structure with three materials as gate electrode was proposed by S. Tiwari et al. [9] to reduce source-to-drain leakage current due to the threshold voltage of the side gates that is smaller than that of the main gate. Co-operating the advantage of gate-stack with straddle-gate structure, R.S. Gupta et al. [10]

suggested a new device structure that is so-called the tri-material gate-stack (TRIMGAS) MOSFET. To precisely analyze the short-channel tri-material gate-stack surrounding-gate MOSFETs when it is applied for the digital circuits, it is mandatory to develop the exactly 2D behavior model.

While digital system design has continually pushed for the increased speed of minimum size devices, analog and digital designers have often employed longer channels to avoid short channel effects (SCEs) and achieve higher voltage gain. In order to model the analog and digital performance of the circuit consist of multiple-gate MOSFET, it is necessary to know how to verify the model with simulator.

Chapter 2

A NEW QUASI-THREE-DIMENSIONAL SUBTHRESHOLD CURRENT MODEL FOR

SHORT-CHANNEL JUNCTIONLESS TRI-GATE MOSFETs WITH INTERFACE

TRAPPED CHARGES

2.1 Introduction

Being superior to conventional planar MOSFETs, the multiple-gate (MG) MOSFETs with the strong field confinement, prominent volume conduction, better short-channel characteristics, and high packing density can be the promising candidates for the future CMOS application [1]. The junction depth between the source/drain and channel that is inherent in the conventional junction-based MOSFETs strictly limits the further scaling for the VLSI device. Instead of the junction-based (JB) device, the junctionless (JL) transistor is hence proposed to fulfill the nanometer device scaling [11]

[12].

By taking advantage of both JL and MG device structures, the junctionless MG (JLMG) transistor should be the viable alternative to junction-based MG (JBMG) device for the future circuit application [13]. To utilize this novel device of JLMG transistor for the circuit application, it is mandatory to develop a feasible device model.

Previous studies have modeled the JBMG [14] [15] and JLMG devices [16] [17], but there are very few investigations on the subthreshold current model for the tri-gate (TG) MOSFETs. Especially, none of them focused on the subthreshold current model for the JLTG MOSFET by accounting for the interface trapped charge effects (ITCEs). The

interface trapped charges that are unexpectedly induced in the fabrication process can seriously degrade the device performance, such as threshold voltage shift [18], transconductance reduction [19] and drain current degradation [20]. Although M. S.

Kim et al [21][22] have used the subthreshold characteristics to extract the interface trapped charges for the MOS device, however, their studies lacked the physical device model to support how the subthreshold behavior is influenced by the interface trapped charge effects (ITCEs). Moreover, our previously derived trapped-charge-induced subthreshold current model for both JB surrounding-gate (JBSRG) [23] and JB quadruple-gate (JBQG) [24] MOSFETs failed to investigate the subthreshold current degradation of the JLTG MOSFET because the JLTG MOSFET has the different conduction mode in comparison to both JBQG and JBSRG devices. In this work, by accounting for the effects of interface trapped charges on the flat-band voltage, quasi-3D scaling equation, and Pao-Sah’s integral, we propose a novel subthreshold current model for the JLTG MOSFETs to examine the ITCEs. The proposed model thoroughly investigates how the interface trapped charges with different polarities, damaged zones, gate oxide thicknesses, and stressed lengths near the drain side, trapped charge densities, channel length, drain voltages, and silicon thicknesses affect the subthreshold current degradation. The proposed model is verified by the three-dimensional numerical simulation DESSIS of ISE-TCAD and explicitly illustrates how the various interface trapped charge conditions and the device structure parameters affect the subthreshold current behavior. In addition to giving the physical insight into the device physics, the model can be easily used to explore the trapped-charge-induced subthreshold current degradation for the fully depleted JLTG MOSFET for its memory circuit application.

2.2Model Description

The schematic of the 3D tri-gate (TG) MOSFETs are shown in Fig.2.2.1 (a). With cut-plane along with AA’ and BB’, the 2D structure is used to develop the model as shown in Fig.2.2.1 (b) and Fig.2.2.1 (c). With various trapped charge distributions, the channel can be divided into three regions. Regions 1 and 3 denote undamaged zone, and region 2 is damaged zone.

Fig.2.2.1 Schematic of tri-gate MOSFETs: (a) three-dimensional device structure. With cut plane along AA’ and BB’, the device can be equivalently composed of two-dimensional single-gate (SG) MOSFET as shown in (b) and double-gate (DG) MOSFET as shown in (c). The two-dimensional device structures of Fig.2.2.1 (b) and Fig.2.2.1 (c) are used to derive the model, where regions 1, 3, and 2 denote the fresh and damaged zones, respectively.

2.3 Model Derivation

Through the 3D numerical simulation results shown in Fig. 2.3.1 and Fig. 2.3.2, it demonstrates that the inversion carriers density primarily concentrate around the bottom-central position (i.e., (x,y,z)=(tsi/2, -tsi, z)) when the device is in the subthreshold operation regime. As a result, the bottom-central potential will be used to derive the threshold voltage model. By accounting for equivalent of gates (ENG) and assuming the corner effects can be negligible for the small-geometry device in the subthreshold operation regime, the channel potential in the bottom-central location that corresponds to the leakiest path should satisfy the following quasi-3D scaling equation [25]:

2 of gates (ENG) and natural lengths for single-gate (SG), double-gate (DG) and triple-gate (TG) devices, respectively, Nd is the uniform doping concentration of the silicon film, tox is the gate oxide thickness, tsi is the silicon thickness, εsi is the dielectric constant of silicon (εsi =11.7×8.85×10^-14 ), εox is permittivity of oxide (εox =3.9×8.85×10

-14), COX (=εox/tox) is the gate oxide capacitance per unit area, Lg is the device channel

length, and the y-axis is perpendicular and the z-axis is parallel to the channel length, respectively. With the three sides of the gate surrounding the channel, the TG device can suppress SCEs more efficiently than SG and DG MOSFET [26]. In equation (2.3.3), the subscript of i =1, 3, and 2 denotes the fresh and the damaged regions as shown in, ψ

BC,i is bottom-central potential for the long-channel device, and Vfb,1=Vfb,3 is the flat-band voltage in the fresh region.

V_ds = 0 V Vgs = 0.5 V L_g = 50 nm L_s = 0 nm Ld = 0 nm t_si = 20 nm t_ox = 2 nm Nd = 1x10^-18 cm^-3

High Electron Density

Fig. 2.3.1: The 2D distribution of the inversion carrier density for the JLTG FET operating in the subthreshold regime. The high electron density is distributed at the bottom-central location. (Simulation parameters: Vds=0V, Vgs=0.5V, H=W=20 nm, tox=2nm, Lg=50 nm, Nd=1.0x10¹⁸cm^-3)

Fig. 2.3.2: The 3D distribution of the inversion carrier density for the JLTG FET operating in the subthreshold regime. The high electron density is distributed at the bottom-central location. (Simulation parameters: Vds=0V, Vgs=0.5V, H=W=20 nm, tox=2nm, Lg=50 nm, Nd=1.0x10¹⁸cm^-3)

Due to the effect of equivalent oxide charges on the flat-band voltage, the flat-band voltage in the damaged region can be expressed by [27]:

2 1 0 1

1 ( )

[ ^tox ] ^f

fb fb it fb

ox ox ox

x x qN

V V dx Q V

C t C

= −

∫

ρ + = − ^(2.3.4)

Where ρ(x) is localized oxide charge density assumed zero for simplicity, Cox is the gate oxide capacitance per unit area, and Qit=qNf is the uniform interface trapped charge density. The general solution of (2.3.1) is

, ( )= ^{JLTG JLTG} ,

z z

BC i z a ei ^λ b ei ^−λ φBC i

Φ + + (2.3.5)

According to the continuity of both electric field and potential at the boundary conditions at damaged/fresh regions, source/silicon and drain/silicon junctions, ai and bi

in (2.3.5) can be obtained as long-channel central potential in both fresh and damaged regions, respectively. The minimum bottom-central potential in (2.3.5) can be obtained as

, ,min 2 ,

BC i a bi i φBC i

Φ = + (2.3.12)

Assume that the potential of Φi(x=tsi/2,y,z) can be expressed as

2

, Where ΦSC,i(z) and ΦBC,i(z) is the surface-central and bottom-central potentials.

Vfb,i and Vbfb are the front and back flat-band voltages. tbox and tox are the front and back gate oxide thicknesses. Vgs and Vsub are the front and substrate gate biases. We assume the back gate oxide thickness is infinite here. By substituting (2.3.13) into (2.3.14) the C0, C1, and C2 should satisfy the following equation: Φi(x=tsi/2,y,z) that dominates the subthreshold behavior can be written as a function of

ΦBC,i(z), i.e.

, , , 2

( / 2, , ) ( ( ) ) ( ( ) ) ( ( ) )

i x tsi y z A BC i z Bi C BC i z D yi E BC i z F yi

Φ = = Φ + + Φ + + Φ + (2.3.19)

By substituting (2.3.12) into (2.3.19), the minimum channel potential along y direction can be obtained as

, ( ) ( , , ) ( , , ) ( , , ) 2

i min y A BC i min Bi C BC i min D yi E BC i min F yi

Φ = Φ + + Φ + + Φ + (2.3.20)

With the drift-diffusion approach, the charge-trapped current density for JLTG MOSFET can be expressed by

,min

Where ni,min(y, z) is the electron density at the virtual cathode, Nd is the bulk doping density and Φn(z) is the electron quasi-Fermi potential. By integrating (2.3.21) in x and y coordinates, in which (2.3.22) is inserted into the Pao-Sah’s integral, the subthreshold current along z direction can be determined as

,min integrating (2.3.23) along z direction, the subthreshold current can be obtained by

,min

, , , ,

( )

( )

i BC i min i

i BC i min i

G C D

H E F

= − Φ +

= − Φ + (2.3.25)

and erf(x) is the error function. In equation of (2.3.24), the smallest Ids,i (=Ids,damaged) will dominate the subthreshold current for fully depleted JLTG FET with the interface trapped charges. Interface-Trapped-Charge Subthreshold Current Degradation (ITSUBD) is defined by the difference between the fresh and damaged devices for their subthreshold currents in logarithm scales (i.e., ITSUBD = Log[Ids,damaged]-Log[Ids,fresh]) where Ids,damaged and Ids,fresh are the subthreshold current for damaged and fresh devices, respectively.

2.4 Results and Discussion

We used the 3D device simulator "DESSIS" [28] to validate the proposed model.

With the fixed positive/negative trapped charges, Fig. 2.4.1 plots ITSUBD versus normalized damaged zone Ld/Lg for different silicon film thicknesses. Increased the Ld/Lg can further enhance ITSUBD for both positive and negative trapped charges. A thick silicon film of tsi=40 nm is desirable for reducing the ITSUBD caused by the both positive and negative trapped charges. Fig. 2.4.2 shows ITSUBD with Ld/Lg for different gate oxide thicknesses. Irrespective of the polarities for the trapped charges, tox=1 nm induces a smaller ITSUBD than tox=2 nm and 3 nm. Although a thin gate oxide is needed to make the device suffer less ITSUBD, it may initiate the oxide leakage current due to the tunneling effects, which will cause the static power consumption. The trade-off regarding how to reduce ITSUBD without inducing the gate leakage current caused by the tunneling effects should be taken into account as the thin gate device is applied for memory circuits. Fig. 2.4.3 plots ITSUBD versus normalized damaged zone for different stressed lengths near the drain side. The ITSUBD is increased when Ls is increased, which implies that for the fixed channel length, the device will suffer severe ITSUBD when the damaged zone Ld keeps away from the drain side corresponding to the increased Ls. Fig. 2.4.4 plots ITSUBD versus normalized damaged zone for different channel lengths. Although the channel device shows worse immunity to short-channel effects (SCEs), it suffers less ITSUBD caused by the ITCEs than the long-channel device when the normalized damaged zone is increased. On the contrary, the long-channel device suffers more ITSUBD caused by ITCEs than the short-channel device. Fig. 2.4.5 plots ITSUBD as a function of Ld/Lg for different drain voltages Vds. As opposed to SCEs, the larger Vds can reduce more ITCEs that improve the ITSUBD more efficiently than the smaller Vds. Although the enhanced SCEs in Fig. 2.4.1, Fig.

2.4.4, and Fig. 2.4.5 can alleviate ITSUBD more efficiently, the physical insight into the device physics is that when the SCEs are enhanced by the choice of device dimensions and drain voltage, the virtual cathode (i.e., the location of the leakiest path) will move toward the source side [29][30], which hence increases the distance between the damaged zone and the virtual cathode and the impact of the interface trapped charges (i.e., ITCEs) on the short-channel subthreshold current degradation (i.e., ITSUBD) can be expected to be reduced due to the enlarged distance from the virtual cathode to damaged zone. Fig. 2.4.6 plots ITSUBD versus normalized damaged zone for different trapped charge densities. The more trapped charge density the device has, the more ITSUBD the device will encounter. Fig. 2.4.7 plots subthreshold current roll-up versus the channel length for both damaged and fresh devices. The subthreshold current roll-up (SUBRUP) is defined by the difference between the long-channel and short-channel devices for their subthreshold currents in logarithm scales. (i.e., SUBRUP =Log[Ids,short ]-Log[Ids,long]). As the channel length is reduced, the damaged device with negative trapped charges suffers less short-channel effects (SCEs) and has a smaller SUBRUP than the fresh device. In contrast to the negative trapped charges, the positive trapped charges can enhance SCEs and cause the damaged device more SUBRUP than the fresh device when the channel length is further decreased. The ITSUBD versus Ld/Lg for the different device structures, including JLDG, JLTG, and JLQG transistors, is demonstrated in Fig. 2.4.8. It shows that the JLDG device can resist ITSUBD more efficiently than both JLQG and JLTG devices when Ld/Lg is increased. As opposed to SCEs, JLQG device rather than JLDG device will suffer severe ITSUBD induced by ITCEs. Being similar to Fig. 2.4.1, Fig. 2.4.4, and Fig. 2.4.5, since JLDG FET suffers more SCEs than both JLQG and JLTG FETs, it will be the best among the three FETs in resisting ITCEs that brings about the severe ITSUBD. Although the quantum mechanics effects (QMEs) are not included in the present model, the ITSUBD in the QM case

should be identical to it in the classical case because both damaged and fresh device experience the same QMEs.

-4 -2 0 2 4

IT S U BD (A)

0 0.2 0.4 0.6 0.8 1

Normalized Damaged Zone, L

_d

/L

_g

Solid Line:Damaged device with +Nf Dash Line:Damaged device with -Nf Line : Model

Symbol : ISE -&- : t_si= 20 nm -,- : tsi= 30 nm -2- : t_si= 40 nm

V_ds = 0.05 V V_gs = 0.2 V t_ox = 1 nm L_g = 50 nm L_s = 0 nm N_d = 1x10¹⁸ cm^-3 N_f = 1x10¹² cm^-2

Fig. 2.4.1: ITSUBD versus normalized damaged zone for different silicon body thicknesses.

-8

Normalized Damaged Zone, L

_d

/L

_g

Solid Line:Damaged device with +Nf Dash Line:Damaged device with -Nf Line : Model

Fig. 2.4.2: ITSUBD versus normalized damaged zone for different gate oxide thicknesses.

Normalized Damaged Zone, L

_d

/L

_g

Solid Line:Damaged device with +Nf Dash Line:Damaged device with -Nf Line : Model

Fig. 2.4.3: ITSUBD versus normalized damaged zone for different stressed near the drain side Ls.

-8

Normalized Damaged Zone, L

_d

/L

_g

Solid Line:Damaged device with +Nf Dash Line:Damaged device with -Nf Line : Model

Fig. 2.4.4: ITSUBD versus normalized damaged zone for different channel lengths.

-6

Normalized Damaged Zone, L

_d

/L

_g

Solid Line:Damaged device with +Nf Dash Line:Damaged device with -Nf Line : Model

Fig. 2.4.5: ITSUBD versus normalized damaged zone for different drain bias.

-8

Normalized Damaged Zone, L

_d

/L

_g

Solid Line:Damaged device with +Nf Dash Line:Damaged device with -Nf Line : Model

Fig. 2.4.6: ITSUBD versus normalized damaged zone for different uniform interface trapped charge density.

-4

Channel Length (nm), L

_g

Line : Model Symbol : ISE

-&- : Damaged Device with +Nf

-,- : Fresh Device

Fig. 2.4.7: Subrup versus gate length for both fresh and damaged devices.

-8 -4 0 4 8

IT S U BD (A)

0 0.2 0.4 0.6 0.8 1

Normalized Damaged Zone, L

_d

/L

_g

Solid Line:Damaged device with +Nf Dash Line:Damaged device with -Nf Line : Model

Symbol : ISE

-_&- : Double-Gate

-,- : Triple-Gate -2- : Quadruple-Gate

V_ds = 0.05 V V_gs = 0.2 V t_ox = 3 nm t_si = 30 nm L_g = 50 nm L_s = 0 nm N_f = 1x10¹² cm^-2 N_d = 1x10¹⁸ cm^-3

Fig. 2.4.8: ITSUBD versus normalized damaged zone for different device structures, including JLDG, JLTG, and JLQG MOSFETs.

Chapter 3

TWO-DIMENSIONAL SUBTHRESHOLD BEHAVIOR MODEL FOR

SURROUNDING-GATE MOSFETs WITH INTERFACE TRAPPED CHARGES

3.1 Quasi-2D Subthreshold Behavior Model for

Surrounding-Gate MOSFETs with Interface Trapped Charges

3.1.1 Introduction

ITRS has revealed that the implantations of non-classical CMOS structures are needed to overcome the difficult challenges when the semiconductor technology node is below 16 nm [1]. It also indicates that the multiple-gate (MG) MOSFETs with the strong field confinement, prominent volume conduction, and high packing density can be the promising candidates for the future CMOS application. Several literatures have reported that the novel structures for the surrounding-gate (SRG) MOSFETs with the high performance and scalability can be used for the memory DRAM cell [14]. To utilize this device for the memory cell application, it is mandatory to develop a feasible model. Although a numerous of literatures have modeled the drain current for the MG devices [31], [32], there are no investigations on the subthreshold current model for the surrounding-gate (SRG) MOSFETs with the interface trapped charges. In this letter, by accounting for the effects of interface trapped charges on the flatband voltage, we propose a compact subthreshold current model for the SRG MOSFETs with the

interface trapped charges based on the scaling equation and drift-diffusion approach.

The proposed model explicitly illustrates how the interface trapped charges with different polarities, damaged zone lengths, gate oxide, and silicon body thicknesses affect the subthreshold current degradation.

Hot-carrier effects that bring about the accumulated interface trapped charges will degrade the device/circuit performance [33], [3]. A number of literature works have modeled the hot-carrier-induced threshold voltage of planar and double-gate MOSFETs in the past decade [4], [5]. However, the wrong eigenvalue of k for the potential developed by the double-gate model [4] could mislead the device physics. Surrounding-gate MOSFETs showing better scaling length are more promising than both planar and double-gate MOSFETs for future VLSI circuits. Until now, there have been few papers investigating the threshold-voltage model of surrounding-gate MOSFETs with trapped charges [34]. In this chapter, by considering the effects of equivalent oxide charges on flatband voltage [27], a compact analytical threshold-voltage model for surrounding-gate MOSFETs with interface trapped charges is developed. The proposed model is

Hot-carrier effects that bring about the accumulated interface trapped charges will degrade the device/circuit performance [33], [3]. A number of literature works have modeled the hot-carrier-induced threshold voltage of planar and double-gate MOSFETs in the past decade [4], [5]. However, the wrong eigenvalue of k for the potential developed by the double-gate model [4] could mislead the device physics. Surrounding-gate MOSFETs showing better scaling length are more promising than both planar and double-gate MOSFETs for future VLSI circuits. Until now, there have been few papers investigating the threshold-voltage model of surrounding-gate MOSFETs with trapped charges [34]. In this chapter, by considering the effects of equivalent oxide charges on flatband voltage [27], a compact analytical threshold-voltage model for surrounding-gate MOSFETs with interface trapped charges is developed. The proposed model is

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