Chapter 6 INVESTIGATEION OF SURROUNDING-GATE MOSFETs FOR CIRCUIT
6.2 Investigation of Surrounding-Gate MOSFETs for Digital Circuit Application: SRAM
6.2.2 Simulation Result and Discussion
The DESSIS of ISE-TCAD predicted butterfly curve of the surrounding-gate (SRG) MOSFET SRAM cell with VDD = 1.0 V is shown in Fig. 6.2.2. Note that excellent static noise margin (SNM = 369 mV) of SRG MOSFET is obtained. For comparison, we also show in the same figure of butterfly plots predicted with double- and triple-gate MOSFET SRAM cell.
As we have noted, the diameters of silicon body tsi is a crucial parameter in the SRG MOSFET design, and it has been thinned to near its technological limit. To check effects of variations of tsi on the SRG MOSFET SRAM performance, we vary it from 10 nm to 40 nm, and obtain the butterfly curves shown in Fig. 6.2.3 (a). Remember that increasing tsi does not strongly affect ION of the SRG MOSFET, but does increase IOFF
and lower VTH due to the deteriorating SCEs with less quantization in the constituent FDFET. This deterioration is reflected in Fig. 6.2.3 (a) by the degraded SNM of the cell for increasing tsi, which is plotted in Fig. 6.2.3 (b). The SNM is excellent (>350 mV) for the thin tsi, for which the SCE control in the FDFET keeps the SRG MOSFET VTH at its proper value. However, for increasing tsi, it degrades at a rate of 5.5mV/nm as VTH is lowered, despite the sustained relative strength of the SRG MOSFETs. This loss of SRAM performance correlates with the increased IOFF. The tsi variation not only affects SNM, but governs the static power consumption of the cell as well. To show its significance in this regard, we include in Fig. 6.2.3 (b) to calculate the average static power per cell (Pstatic) versus tsi at VDD = 1.0 V. These calculations follow from the fact that in the idle or precharge phase of the SRAM cell [73].
( ) ( )
[ ]
static DD OFF N OFF P
P =V I +I (6.2.1)
We have ignored gate-tunneling leakage, assuming it is well controlled. In the hold
phases of the cell, (6.2.1) can be representative of static power consumption per cell averaged over a memory array.
Lower VDD can be used to reduce Pstatic, at the expense of lower SNM due to the smaller difference between the inverter switch-point voltage and VDD [71]. For tsi = 20 nm, the butterfly curves of the SRG MOSFET SRAM cell with decreasing VDD shown in Fig. 6.2.4 (a) reveal the SNM degradation. For each VDD assumed, the predicted SNM versus tsi is plotted in Fig. 6.2.4 (b), along with those for the SRG MOSFET SRAM.
O u tp ut Voltage , V
out(V )
tox = 3 nm
Fig. 6.2.2: The butterfly curve with different device structure for comparison.
tsi = 10 nm
Output Voltage, Vout (V)
tox = 3 nm
Diameters of Silicon Body, tsi (nm) 0
Fig. 6.2.3: (a) The butterfly curve of surrounding-gate MOSFET with different diameters of silicon body. (b) The SNM extracted from (a), alone with average static power consumption of SRAM cell, versus different diameters of silicon body.
Vdd = 0.4 V
Diameters of Silicon Body, t
si(nm) 150
Fig. 6.2.4: (a) The butterfly curve of surrounding-gate MOSFET with different supply voltage. (b) The SNM extracted from (a) for each VDD versus diameters of silicon body.
6.2.3 Conclusion
The SRG MOSFET could have widespread applications, especially in circuits that require device rationing. A good example is the SRG MOSFET 6T-SRAM cell, it can ensure cell stability. To quantize it, the static noise margin is a critical metric for SRAM bitcell stability. This section has explored the impact of different parameters on SNM for SRAM bitcells with the simulation of DESSIS of ISE-TCAD. Results also highlight that SRG MOSFET is also beneficial for superior digital performance in terms of higher static noise margin and shows the trade off between power consumption and static noise margin with different supply voltage.
Chapter 7
Conclusions and Future Works
7.1 Conclusion
Based on the parabolic and exact solution of the Poisson equation, an analytical subthreshold model for the SRG MOSFETs with interface trapped charges have been developed by considering the effects of equivalent oxide charges on the flat-band voltage. It also includes junction-based and junctionless MOSFET. Further, based on the exact solution of 2D Poisson equation, the analytical model comprising channel potential, threshold voltage, subthreshold swing and subthreshold current for JLTMGSRG MOSFETs have been developed.
In last chapter, we also introduce the circuit application with surrounding-gate as a glance. The analog and digital performances of TMSRG and SRG have been demonstrated, respectively.
7.2 Future Works
The trend towards thinner channel and shorter gate length is resulting in increased importance of quantum effects. At nanoscale-dimensions, there is a need to imagine the carriers as particle-waves rather than semi-classical particle and it becomes imperative to study the electron confinement in the channel by considering quantum mechanical effects (QMEs). Those mentioned-above classical models can be well extended to quantum-mechanical model for SRG device by considering effective oxide thickness effects and band-gate widening effects.
Finally, all of the potential, threshold voltage, and subthreshold current models can be further extended the subthreshold logic circuit models when the SRG devices are
applied for low-power circuits.
References
[1] ITRS – International Technology Roadmap for Semiconductor, Edition 2012.
[2] J. P. Colinge, C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A. M. Kelleher, B. McCarthy and R. Murphy,
“Nanowire transistors without junctions,” Nature Nanotechnology, vol. 5, pp. 225-229, Feb. 2010.
[3] E. Amat, T. Kauerauf, R. Degraeve, A. De Keersgieter, R. Rodriguez, M. Nafria, X.
Aymerich, and G. Groeseneken, “Channel hot-carrier degradation in short-channel transistors with high-k/metal gate stacks,” IEEE Transactions on Device and Materials Reliability, vol. 9, no. 3, pp. 425-430, Sep. 2009.
[4] H. Kang, J. W. Han, and Y. K. Choi, “Analytical threshold voltage model for double-gate MOSFET with localized charges,” IEEE Electron Device Letter, vol.
29, no. 8, pp. 927-930, Aug. 2008.
[5] Y. S. Jean and C. Y. Wu, “The threshold-voltage model of MOSFET devices with localized interface charge,” IEEE Transactions on Electron Devices, vol. 44, no. 3, pp. 441-447, Mar. 1997.
[6] X. Zhou, W. Long, “A novel hetero-material gate (HMG) MOSFET for deepsubmicron ULSI technology,” IEEE Transactions on Electron Devices, vol.
45, no. 12, pp. 2546-2548, Dec. 1998.
[7] Q. Lu, D. Park, A. Kalnitsky, C. Chang, C. Cheng, S. P. Tay, T. -J. King, and C. Hu,
“Leakage current comparison between ultra-thin Ta2O5 films and conventional gate dielectrics,” IEEE Transactions on Electron Devices Letter, vol. 19, no. 9, pp.
341-342, Sep. 1998.
[8] B. H. Lee, S. C. Song, R. Choi, and P. Kirsch, “Metal electrode/high-k dielectric gate-stack technology for power management,” IEEE Transactions on Electron Devices, vol. 55, no. 1, pp. 8-20, Jan. 2008.
[9] S. Tiwari, J. J. Welser, A. Kumar, and S. Cohen, “Straddle gate transistors: high Ion/Ioff transistors at short gate lengths,” 1999 Device Research Conference Digest, pp. 26-27, Jun. 1999.
[10] K. Goel, M. Saxena, M. Gupta, and R. S. Gupta, “Modeling and simulation of a nanoscale three-Region tri-material gate stack (TRIMGAS)MOSFET for improved carrier transport efficiency and reduced hot-electron effects,” IEEE Transactions on Electron Devices, vol. 53, no. 7, pp. 1623-1633, Jul. 2006.
[11] C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, and J.-P. Colinge,
“Junctionless multigate field-effect transistor,” Journal of applied physics Letter, vol. 94, no. 5, pp. 053511-1-053511-2, Feb. 2009.
[12] S. Gundapaneni, S. Ganguly, and A. Kottantharayil, “Bulk Planar Junctionless
Transistor (BPJLT): An Attractive Device Alternative for Scaling,” IEEE Electron Devices Letter, vol. 32, no. 3, pp. 261-263, Mar. 2011.
[13] E. Gnani, A. Gnudi, S. Reggiani, and G. Baccarani, “Theory of the junctionless nanowire FET,” IEEE Transactions on Electron Devices, vol. 58, no. 9,pp. 2903-2910, Sept. 2011
[14] B. Yu, J. Song, Y. Yuan, W.Y. Lu, and Y. Taur, “A unified analytic drain-current model for multiple-gate MOSFETs”, IEEE Transactions on Electron Devices, vol.
55, no. 8, pp. 2157-2163, Aug. 2008.
[15] J. P. Duarte, S. J. Choi, D. I. Moon, J. H. Ahn, J. Y. Kim, S. Kim, and Y. K. Choi,
“A universal core model for multiple-gate field-effect transistors. Part II. Drain current model, ” IEEE Transactions on Electron Devices, vol. 60, no. 2, pp. 848-855, Feb. 2013.
[16] C. Li, Y. Zhuang, S. Di, and R. Han, “Subthreshold Behavior Models for Nanoscale Short-Channel Junctionless Cylindrical Surrounding-Gate MOSFETs,”
IEEE Transactions on Electron Devices, vol. 60, no. 11, pp. 3655-3662, Nov. 2013.
[17] G. Hu, P. Xiang, Z. Ding, R. Liu, L. Wang, and T. A. Tang, “Analytical Models for Electric Potential, Threshold Voltage, and Subthreshold Swing of Junctionless Surrounding-Gate Transistors,” IEEE Transactions on Electron Devices, vol. 61, no. 3, pp. 688-694, Mar. 2014.
[18] A. Bekaddour, M. G. Pala, N. Chabane-Sari, and G. Ghibaudo, ”Deterministic Method to Evaluate the Threshold Voltage Variability Induced by Discrete Trap Charges in Si-Nanowire FETs,” IEEE Transactions on Electron Devices, vol. 59, no. 5, pp. 1462-1467, May. 2012.
[19] D. S. Ang, ”A New Insight Into the Degradation Behavior of the LDD N-MOSFET During Dynamic Hot-Carrier Stressing,” IEEE Electron Devices Letter, vol. 22, no.
11, pp. 553-555, Nov. 2001.
[20] X. Y. Huang, G. F. Jiao, W. Cao, D. Huang, H. Y. Yu, Z. X. Chen, N. Singh G. Q.
Lo, D. L. Kwong, and Ming-Fu Li, ”Effect of Interface Traps and Oxide Charge on Drain Current Degradation in Tunneling Field-Effect Transistors,” IEEE Electron Devices Letter, vol. 31, no. 8, pp. 779-781, Aug. 2010.
[21] M. S. Kim, I. C. Nam, H. T. Kim, H. T. Shin, T. E. Kim, H. S. Park, K. S. Kim, K.
H. Kim, J. B. Choi, K. S. Min, D. J. Kim, D. W. Kang and D. M. Kim, “Optical Subthreshold Current Method for Extracting the Interface States in MOS Systems,”
IEEE Electron Device Letter, vol. 25, no. 2, pp. 101-103, Feb. 2004.
[22] J. He, X. Zhang, R. Huang, and Y. Wang, “Linear cofactor difference method of MOSFET subthreshold characteristics for extracting interface traps induced by gate oxide stress test,” IEEE Transactions on Electron Devices, vol. 49, no. 2, pp.
331-334, Feb. 2002.
[23] T. K. Chiang, ”A Compact Interface-Trapped-Charge-Induced Subthreshold Current Model for Surrounding-Gate (SRG) MOSFETs,” IEEE Transactions on Device and Materials Reliability, vol. 14, no. 2, pp. 766-768, Jun. 2014.
[24] T. K. Chiang, “A New Interface-Trapped-Charge-Degraded Subthreshold Current Model for Quadruple-Gate (QG) MOSFETs,” IEEE Transactions on Electron Devices, vol. 61, no. 5, pp. 1611-1614, May 2014.
[25] T. K. Chiang, “A Novel Scaling Theory for Fully-Depleted, Multiple-Gate MOSFET, Including Effective Number of Gates (ENG),” IEEE Transactions on Electron Devices, vol. 61, no. 2, pp. 631-633, Feb. 2014.
[26] J. T. Park and J. P. Colinge, “Multiple-Gate SOI MOSFETs: Device Design Guidelines,” IEEE Transactions on Electron Devices, vol. 49, no. 12, pp. 2222-2229, Dec. 2002.
[27] Y. Taur and T. H. Ning, ”Fundamentals of Modern VLSI Devices,” Cambridge University Press, 2002.
[28] “DESSIS”: 2D/3D device simulator, Integrated Systems Engineering, Synopsis, 2003.
[29] Z. Yuan and Z. Yu, “Short-Channel-Effect Modeling of DG-FETs Using Voltage-Doping Transformation Featuring FD/PD Modes,” IEEE Electron Device Letters, vol. 30, no. 11, pp. 1209-1211, Nov. 2009.
[30] D. Sharma and S. K. Vishvakarma, “Precise Analytical Model for Short-Channel Quadruple-Gate Gate-All-Around MOSFET,” IEEE Transactions on Nanotechnology, vol. 12, no. 3, pp. 378-385, May 2013.
[31] T. Kadowaki, Y. Yamakawa, H. Nakamura, Kamura, Yauso, M. Niwano, and F.
Masuoka, “A new architecture for high-density high performance SGT nor flash memory,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 55, no. 6, pp. 551-555, Jun. 2006.
[32] F. Liu, J. He, L. Zhang, and J. Zhang, “A charge-based model for long channel cylindrical surrounding-gate MOSFETs from intrinsic channel to heavily doped body,” IEEE Transactions on Electron Devices, vol. 55, no. 8, pp. 2187-2194, Aug.
2008.
[33] Y. Toyota, M. Matsumura, M. Hatano, T. Shiba, and M. Ohkura, “Degradation characteristics of n- and p-channel polycrystalline-silicon TFTs under CMOS inverter operation,” IEEE Transactions on Electron Devices, vol. 57, no. 2, pp.
429-436, Feb. 2010.
[34] H. J. Cho and J. D. Plummer, “Modeling of surrounding gate MOSFETs with bulk trap states,” IEEE Transactions on Electron Devices, vol. 54, no. 1, pp. 166-169, Jan. 2007.
[35] T. K. Chiang, “A new quasi-2D threshold voltage model for short-channel
Junctionless (JL) cylindrical surrounding-gate MOSFET,” IEEE Transactions on Electron Devices, vol. 59, no. 11, pp. 3127-3129, Nov. 2012.
[36] T. K. Chiang, “A new scaling theory for fully-depleted SOI double-gate MOSFETs: Including Effective Conducting Path Effect (ECPE),” Solid-state electronics, vol. 49, no. 3, pp. 317-322, Mar. 2005.
[37] M. J. Kumar, A. A. Orouji, and H. Dhakad, “New dual-material SG nanoscale MOSFET: Analytical threshold-voltage model,” IEEE Transactions on Electron Devices, vol. 53, no. 4, pp. 920-923, Jan. 2006.
[38] T. K. Chiang, “New Analytical Model for Short-Channel Fully Depleted Dual-Material Gate Silicon-on-Insulator Metal Semiconductor Field-Effect Transistor,”
Japanese Journal of Applied Physics, vol. 47, no. 12, pp.8743-8748, Dec. 2008.
[39] K. Suzuki, Y. Tosaka, and T. Sugii, “Analytical threshold voltage model for short channel double gate MOSFET’s,” IEEE Transactions on Electron Devices, vol. 43, no. 7, pp. 732-738, Jul. 1996.
[40] T. K. Chiang, “A compact, analytical two-dimensional threshold voltage model for cylindrical, fully-depleted, surrounding-gate (SG) MOSFETs,” Semiconductor science and technology, vol. 20, no. 12, pp. 1173-1178, Dec. 2005.
[41] T. K. Chiang, “A new two-dimensional analytical subthreshold behavior model for short-channel tri-material gate-stack SOI MOSFETs,” Microelectronics Reliability, vol. 49, no. 2, pp. 113-119, Feb. 2009.
[42] C. Li, Y. Zhuang, R. Han and G. Jin, “Subthreshold Behavior Models for Short-Channel Junctionless Tri-Material Cylindrical Surrounding-Gate MOSFETs,”
IEEE Transactions on Electron Devices, vol. 60, no. 11, pp. 3655-3662, Nov. 2013.
[43] V. P. Privepi and J. G. Fossum, “Quantum mechanical effects on the threshold voltage of undoped double-gate MOSFETs,” IEEE Transactions on Electron Devices, vol. 26, no. 8, pp. 579-582, Aug. 2005.
[44] G. V. Reddy, and M. J. Kumar, “A new dual-material double-gate (DMDG) nanoscale SOI MOSFET two-dimensional analytical modeling and simulation”, IEEE Transactions on Electron Devices, vol. 4, no. 2, pp. 260-268, Mar. 2005.
[45] M. Saxena, S. Haldar, M. Gupta, and R.S. Gupta, “Physics-based modeling and simulation of dual material gate stack (DUMGAS) MOSFET,” Electronics Letters, vol. 39, no. 1, pp. 155-157, Jan. 2003.
[46] K. K. Young, “Short-channel effect in fully depleted SOI MOSFETs,” IEEE Transactions on Electron Devices, vol. 36, no. 2, pp. 399-402, Feb. 1989.
[47] M. Saxena, S. Haldar, M. Gupta and R.S. Gupta, “Physics-based analytical modeling of potential and electrical field distribution in dual material gate (DMG)-MOSFET for improved hot electron effect and carrier transport efficiency,” IEEE Transactions on Electron Devices, vol. 49, no. 11, pp.1928-1938, Nov. 2002.
[48] H. Kawaura, T. Sakamoto, T. Baba, Y. Ochiai, J. Fujita, and J. Sone, “Transistor characteristics of 14-nm-gate-length EJ-MOSFETs,” IEEE Transactions on Electron Devices, vol. 47, no. 4, pp. 856-860, Apr. 2000.
[49] J. Wang, P. M. Solomon, M. Lundstrom, “A general approach for the performance assessment of nanoscale silicon FETs,” IEEE Transactions on Electron Devices, vol. 51, no. 9, pp. 1366-1370, Sep. 2004.
[50] J. J. Liou, A. Ortiz-Conde, and F. Garcia-Sanchez, ”Analysis and Design of MOSFETs,” Kluwer Academic Publishers, 2000.
[51] Q. Chen, B. Agrawal, and J. D. Meindl, “A comprehensive analytical subthreshold swing (S) model for double-gate MOSFETs,” IEEE Transactions on Electron Devices, vol. 49, no. 6, pp. 1086-1090, Jun. 2002.
[52] 張鐸瀚、民 101，参材質/雙材質具氧化層基體絕緣結構之三閘極金氧半場效 電晶體和含氧化層介面缺陷電荷之次臨界行為研究，國立高雄大學電機工程 研究所碩士論文。
[53] G. K. Cellera, S. Cristoloveanu, “Frontiers of silicon-on-insulator”, Journal of applied physics, vol. 93, no. 9, pp. 4955-4978, May 2003.
[54] C. H. Wann, K. Noda, T. Tanaka, M. Yoshida, and C. Hu, “A comparative study of advanced MOSFET concepts,” IEEE Transactions on Electron Devices, vol. 43, no. 10, pp. 1742- 1753, Oct. 1996.
[55] D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, H. S. P. Wong,
“Device scaling limits of Si MOSFETs and their application dependencies,”
Proceedings of the IEEE, vol.89, no.3, pp.259-288, Mar. 2001.
[56] B. Ray, S. Mahapatra, “Modeling of Channel Potential and Subthreshold Slop of Symmetric Double Gate Transistor,” IEEE Transactions on Electron Devices, vol.
56, no. 2, pp. 260-266, Feb. 2009.
[57] B. Yu, C. H. J. Wann, E. D. Nowak, K. Noda, and C. Hu, “Short-channel effect improved by lateral channel-engineering in deep-submicronmeter MOSFETs,”
IEEE Transactions on Electron Devices, vol. 44, no. 4, pp. 627-634, Apr. 1997.
[58] P. H. Woerlee, M. J. Knitel, R. van Langevelde, D. B. M. Klaassen, L. F. Tiemeijer, A. J. Scholten, et al. A. T. A., “RF-CMOS performance trends,” IEEE Transactions on Electron Devices, vol. 48, no. 8, pp. 1776-1782, Aug. 2001.
[59] H. S. Momose, E. Monfuzi, T. Yoshitomi, T. Ohguro, M. Saito, T. Morimoto, et al.,
“High frequency AC characteristics of 1.5-nm gate oxide MOSFETs,” 1996 International Electron Devices Meeting (IEDM 1996), pp. 105-108, Dec. 1996.
[60] Y. Momiyama, T. Hirose, H. Kurata, K. Goto, Y. Watanabe, T. Sugii., ”A 140 Ghz fT and 60 Ghz fmax DTMOS integrated with high performance SOI logic technology”, 2000 International Electron Devices Meeting (IEDM 2000), pp. 451-455, Dec. 2000.
[61] S. H. Oh, D. Monroe, and J. M. Hergenrother, “Analytical Description of short-channel effects in fully-depleted double-gate and cylindrical surrounding-gate MOSFETs,” IEEE Transactions on Electron Devices, vol.21, no. 9, pp. 445-447, Sept. 2000.
[62] T. Endoh,, M. Suzuki, H. Sakuraba,, and Fujio Masuok, ”2.4 F2 memory cell technology with stacked surrounding gate transistors (S-SGT) DRAM,” IEEE Transactions on Electron Devices, vol. 21, no. 8, pp. 1599-1603, Aug. 2001.
[63] B. Goebel, J. Lutzen, D. Manger, P. Moll, K. Mummler, M. Popp, U. Scheler, T.
Schlosser, H. Seidl, M. Sesterhenn, S. Slesazeck, and S. Tegen, “Fully-depleted surrounding -gate transistor(SGT) for 70nm DRAM and beyond“, 2002 International Electron Devices Meeting (IEDM 2002), pp. 275-278, Dec. 2002.
[64] J. Yuan and J. C. S. Woo, “Nanoscale MOSFET with split-gate design for RF/analog application,” Japanese Journal of Applied Physics, vol. 43, no. 4B, pp.
1742-1745, Apr. 2004.
[65] M. J. Kumar and A. Chaudhry, “Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs,” IEEE Transactions on Electron Devices, vol. 51, no. 4, pp. 569-574, Apr. 2004.
[66] W. Long, H. Ou, J. -M. Kuo, and K. K. Chin, “Dual-material gate (DMG) field effect transistor,” IEEE Transactions on Electron Devices, vol. 46, no. 5, pp. 865-870, May 1999.
[67] R. Kaur, R. Chaujar, M. Saxena, and R. S. Gupta, “Hot-carrier reliability and analog performance investigation of DMG-ISEGaS MOSFET,” IEEE Transactions on Electron Devices, vol. 54, no. 9, pp. 2556-2561, Sept. 2007.
[68] J. H. Huang, Z. H. Liu, M. C. Jeng, P. K. Ko, and C. Hu, “A physical model for MOSFET output resistance,” 1992 International Electron Devices Meeting (IEDM 1992), pp. 569–572, Dec. 1992.
[69] P. Kasturi, M. Saxena, M. Gupta, R. S. Gupta, “Dual Material Double-Layer Gate Stack SON MOSFET: A Novel Architecture for Enhanced Analog Performance—
Part I: Impact of Gate Metal Workfunction Engineering,” IEEE Transactions on Electron Devices, vol. 55, no. 1, pp. 372-381, Jan. 2008.
[70] E. Morifuji, T. Yoshida, M. Kanda, S. Matsuda, S. Yamada, F. Matsuoka. “Supply and Threshold-Voltage Trends for Scaled Logic and SRAM MOSFETs,” IEEE Transactions on Electron Devices, vol. 53, no. 6, pp. 1427-1432, Jun. 2006.
[71] E. Seevinck Sr., F. J. List, and J. Lohstroh, “Static-noise margin analysis of MOS SRAM cells,” IEEE Journal of Solid-State Circuits, vol. SC-22, no. 5, pp. 748-754, Oct. 1987.
[72] E. Morifuji, T. Yoshida, H. Tsuno, Y. Kikuchi, S. Matsuda, S. Yamada, T. Noguchi, and M. Kakumu, “New guideline of Vdd and Vth scaling for 65 nm technology
and beyond,” 2004 Symposium on VLSI Technology Digest of Technical Papers, pp. 164-165, Jun. 2004.
[73] M. Mamidipaka, K. Khouri, N. Dutt, M. Abadir, “Leakage Power Estimation in SRAMs,” University of California, Irvine, CECS, Technical Report #03-32, Sept.
2003.
Publication List
1. T. K. Chiang, H. W. Gao, C. W. Liu, T. Y. Tsou, Y. H. Chiu, “A new interface-trapped-charge-degraded subthreshold current model for cylindrical, surrounding-gate (CSRG) MOSFETs,” 2014 International Symposium on Next-Generation Electronics (ISNE 2014), Kwei-Shan Tao-Yuan, Taiwan, 7-10 May 2014.
2. T. K. Chiang, H. W. Gao, C. W. Liu, T. Y. Tsou and Y. H. Chiu, “A Novel Scaling Theory for Fully Depleted Pi-Gate (ΠG) MOSFETs,” 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT 2014), Guilin, China, 28-31 Oct. 2014.
3. T. K. Chiang, T. Y. Tsou, and Y. H. Chiu, “A New Quasi-3D Compact Threshold Voltage Model for Pi-Gate (PG) MOSFETs with the Interface Trapped Charges”
2014 International Electron Devices and Materials Symposium (IEDMS 2014), Hualien, Taiwan, 20-21 Nov. 2014.
4. T. K. Chiang, Y. H. Chiu, H. W. Gao, and Y .H. Wong, “A Three Dimensional Analytical threshold Voltage Model for Quadruple Gate MOSFET with the Interface Trapped Charges,” 2014 International Electron Devices and Materials Symposium (IEDMS 2014), Hualien, Taiwan, 20-21 Nov. 2014.
Reward Certificate
VITA
Name: Yi-Hung Chiou Date of Birth: Oct. 27, 1989 Birthplace: Tainan, Taiwan E-mail: [email protected] Phone: +886-912-213-344
Address: no.168, Fu’an, Alian Dist., Kaohsiung City 82242, Taiwan (R.O.C.) Academic record:
1. 2008-2013 (B.S)
Department of Electrical Engineering, National University of Kaohsiung, Taiwan
2. 2013-2015 (M.S)
Institute of Electrical Engineering, Department of Electrical Engineering, National University of Kaohsiung, Taiwan
Thesis Title:
The Investigation on Subthreshold Behavior Model for the Tri-Gate/Surrounding-Gate MOSFETs with the Interface Trapped Charges/Gate-Stack Structure.