Electric Field

Due to rapid advancement in the lithographic technology, the pace at which the physical dimensions have been reduced, but the voltages in the device have not reduced.

It would bring a higher electric field, which also increases current and hot carrier injection into the gate [47]. The junctionless tri-material gate-stack surrounding-gate (JLTMGSRG) MOSFETs structure has high work function M1 near the source side, lowest work function M3 near the drain side. Due to different work-function of two different material gates has produced a step potential and center electric field to improving the gate transport efficiency in the channel. Fig. 5.7.1 illustrates the profile of the electric filed for the junctionless tri-material gate-stack surrounding-gate (JLTMGSRG) MOSFETs with ratio of L1:L2:L3=1:1:1, and the junctionless single-material gate-stack surrounding-gate (JLSMGSRG) MOSFETs are also included for comparison. It is apparent that the peak of the electric field for the devices can be adjusted to spread in between the channel region, which can speed up the carriers to drift across the channel and enhance the carrier transport efficiency. Furthermore, the electrical field at the drain side for the junctionless tri-material gate-stack surrounding-gate (JLTMGSRG) MOSFETs is obviously lower than that for the junctionless single-material gate-stack surrounding-gate (JLSMGSRG) MOSFETs and the HCEs is reduced by the junctionless tri-material gate-stack surrounding-gate (JLTMGSRG) MOSFETs.

Therefore, carrier transport efficiency and device speed are increased in using the junctionless tri-material gate-stack surrounding-gate (JLTMGSRG) [48].

0 15 30 45 60 75 90 105 120 Channel Position, z (nm)

0 0.4 0.8 1.2

Electric Field , |E | (MV/cm )

Line : Model Symbol : ISE V_ds = 0 V V_gs = 0.3 V

t_oxeff = 2 nm t_si = 20 nm L_g = 120 nm N_d = 1x10¹⁸ cm^-3 F_M1 = 5.5 eV F_M2 = 5.0 eV F_M3 = 4.7 eV

-,- : Single Material -&- : L₁:L₂:L₃ = 1:1:1

Fig. 5.7.1: The variation of the electric field alone the channel for the ratio of L1:L2:L3=1:1:1, and the junctionless single-material gate-stack surrounding-gate (JLSMGSRG) MOSFETs are also included for comparison.

5.8 Threshold Voltage Model

The threshold voltage can be considered as the gate bias in which bulk conduction starts to occur. This condition is satisfied when there is a point at the center of the channel that is not depleted. As the source of the device is directly connected to the ground and as there are no junctions, the potential at this point can be considered as zero (ψ_i,min( ) 0r = ).

In order to solve analytical threshold voltage, we need to rewrite coefficients as a linear equation related to VGS. From eq.(5.4.2), eq.(5.4.3) and eq.(5.4.11 ~ 5.4.16), we get

2

By using eq.(5.8.1) ~ eq.(5.8.6), we can get the minimum potential as a linear equation related to gate bias VGS.

( )

1,_i 4 _{i i} 1

T = α η − (5.8.21)

2,_i 2( _{i i i i}) _i

T = α δ β η+ − (5.8.22) k

2

3,_i 4 _{i i i}

T = β δ −k (5.8.23)

2

, 4 16

d d

i FB i si si

oxeff si

qN qN

k V t t

C ε

= − + +

′ (5.8.24)

From eq.(5.8.19), ψ_i,min = , and solving for V0 GS, the threshold voltage can be achieved. Due to reducing the complicated calculation and its rapid decay of Fourier series, choose the first term can dominate the whole series. Thus

2

2, 2, 1, 3,

,

1,

i i i i

TH i

i

T T T T

V T

− + −

= (5.8.25)

The largest VTH,i in above equation will dominate the threshold voltage.

5.9 Threshold Voltage Model Result

Fig. 5.9.1 shows the threshold voltage roll-off versus the channel length Lg with the ratio of L1:L2:L3 as a parameter. It is obviously observed that the high ratio of L1:L2:L3 such as L1:L2:L3=2:1:1 can effectively decrease the threshold voltage roll-off as the channel length is reduced. It is also revealed that the large gate length ratio of L1:L2:L3 will result in slight threshold voltage roll-off in comparison to the small ratios like 1:1:1 and 1:1:2. To effectively repress SCEs and cause less threshold voltage degradation, the large gate length ratio of L1:L2:L3 is preferred. However, the high ratio of L1:L2:L3 will result in large operating threshold voltage that can increase the power dissipation and should be avoided when the device is designed for the low-power circuit. Fig. 5.9.2 shows how the effective gate oxide thickness affects the threshold voltage roll-off. Since the vertical filed for the thin effective gate oxide will reach the channel region more easily than it for the thick one and take the better control of the channel. The plot implies that the gate gradually loses control of the channel as the effective gate oxide steadily increases its thickness, which prevents the vertical electric field from passing through the channel, which brings about severe DIBL. Both thin effective gate oxide thickness and the thin silicon thickness are referred to alleviate the threshold voltage roll-off. To suppress SCEs, the thin effective gate oxide is preferred.

In practice, the effective gate oxide cannot be reduced below a certain limit because the tunneling current will occur. For example, when the thickness is scaled down below 3 nm, the gate tunneling leakage caused by the quantum mechanical effects will come about and degrade the device performance. Fig. 5.9.3 shows the dependence of threshold voltage roll-off on the channel length with silicon film thickness as a parameter. It is revealed that as the silicon film thickness is decreased, the threshold voltage roll-off will increase accordingly. The more thin silicon film will result in the

less threshold degradation. It suggests that the thin film is preferred to suppress the short channel effects as the designing device pushed into sub-micrometer regime. The threshold voltage roll-off predicted by the analytical solution is in good agreement with those from numerical simulation.

30 45 60 75 90 105 120

Channel Length, L

_g

(nm) -0.16

-0.12 -0.08 -0.04 0

Th re sh old V o lt age Roll -of f ( V )

Line : Model Symbol : ISE V_ds = 0.05 V t_oxeff = 2 nm t_si = 10 nm N_d = 1x10¹⁸ cm^-3 F_M1 = 4.8 eV F_M2 = 4.5 eV F_M3 = 4.2 eV -&- : L₁:L₂:L₃ = 2:1:1

-,- : L1:L₂:L₃ = 1:1:1 -/- : L₁:L₂:L₃ = 1:1:2

Fig. 5.9.1: The dependence of threshold voltage roll-off on channel length for different gate material ratios of L1:L2:L3.

30 45 60 75 90 105 120 Channel Length, L

_g

(nm)

-0.08 -0.04 0

Threshold V o ltage R oll -off (V )

Line : Model

Fig. 5.9.2: The dependence of threshold voltage roll-off on channel length for different effective gate oxide thicknesses.

30 45 60 75 90 105 120

Threshold V o ltage R oll -off (V )

Line : Model

Fig. 5.9.3: The dependence of threshold voltage roll-off on channel length for different silicon film thicknesses.

5.10 Subthreshold Current Model

Knowing the minimum channel potential solution of (5.5.2), we can proceed to derive the subthreshold current. Since the current density for the junctionless tri-material gate-stack surrounding-gate MOSFET flows predominantly in the z direction (from source to drain), the electron quasi-Fermi potential is essentially constant in the r-direction and is only function of z. By using the drift-diffusion approach, the current density (both drift and diffusion) together with the electron carrier density at the virtual cathode point can be written as

,min

where ni is the intrinsic carrier density. By integrating (5.10.1) in z and directions, the subthreshold current for the surrounding-gate MOSFET can be obtained as

,min( ) ( )

Since the current is constant along the channel direction of z, integration of (5.10.3) with respect to z from 0 to yields Lg. The general subthreshold current can be expressed as

Because it is too complicated to calculate the integral in eq. (5.10.4), a numerical solution is used to simplify the exponential forms. To obtain the analytical expression, we take advantage of trapezoidal integration rule. Due to the arrangement is such that

the work function of the gate metal near the source is higher than others near the drain in junctionless tri-material gate-stack surrounding-gate MOSFETs that causes region 1 will dominate the subthreshold current. Therefore, the double integrals in eq.(5.10.4) can be rewritten as

1,min( ) 2 ,1

1

(1 ) ,1

si DS

T T

nt

V m m

V V

T d si

sub

g n

V q N t

I e re m

mL

π μ ⁻ ψ

=

= −

∑

≤ ≤ ∞ ^(5.10.5)

Where m is the partition numbers in the interval of [0,tsi/2]. From eq.(5.10.4) and eq.(5.10.5) the analytical subthreshold current model can be theoretically achieved.

5.11 Subthreshold Current Model Result

A larger partition numbers result in the use of more computing power. There should be a compromise between the accuracy and the calculation time when a piecewise straight line replaces the indefinite curve to evaluate the integral. The dependence of the subthreshold current on the gate bias for different ratios of L1:L2:L3 is shown in Fig. 5.11.1. From the plot, the device with a small ratio of L1:L2:L3=1:1:2 can induce a higher subthreshold leakage current than those of devices with large ratios. At the cost of high subthreshold leakage, a device with a small ratio of L1:L2:L3=1:1:2 can provide the circuit with sufficient driving current under saturation operation for VLSI application. Moreover, the large ratio of L1:L2:L3=2:1:1 can suppress subthreshold leakage current at the cost of the large applied threshold voltage. Fig. 5.11.2 illustrates how the effective gate oxide thickness takes effect on the subthreshold current for the varied gate bias. The decrease in effective gate oxide thickness can restrain effectively reduce subthreshold leakage current shown in the figure. Fig. 5.11.3 shows the dependence of subthreshold current on the gate bias with silicon film thickness as a parameter. From the plot, the thin value of tsi=10 nm can have a lower subthreshold leakage current in comparison to those thick silicon bodies. However, regardless of higher subthreshold leakage, those thick silicon bodies can provide sufficient driving current and increase the device speed that causes the less circuit propagation delay when the device is used for low-power circuit application [49]. The trade-off between how to keep low subthreshold degradation and to have high driving capability should be accounted for simultaneously as the device is designed for the circuit application. Fig.

5.11.4 shows the plots of subthreshold current model calculated from eq.(5.10.5) and the data are compared with those simulated from 3D numerical simulator. It is found that the scaling of channel length lead to increasing of subthreshold leakage current due to

the strong SCEs, which will elevate the minimum bottom potential barrier Ψ1min such that the subthreshold current increases dramatically (note that according to eq.(5.10.5), subthreshold current is proportional to and a slight variation of Ψ1min can bring about high subthreshold current). This is consistent with the well-known decrease in subthreshold slope with a decrease in channel length. As gate bias is below the threshold voltage, the subthreshold leakage current will dominate the drain current characteristics which can be depicted by eq.(5.10.5). The Isub-Vgs characteristics simulated from device simulator are in good agreement with the calculated data for different channel length of tri-material single-gate MOSFETs device.

0 0.2 0.4 0.6

Su b thr es h o ld Cu rr en t, I

sub

(A )

Line : Model

Fig. 5.11.1: Analytical solution of the subthreshold current for junctionless tri-material surrounding-gate gate-stack MOSFETs compared with 3D numerical simulation results for different ratios of L1:L2:L3.

0 0.2 0.4 0.6

Su b thr es h o ld Cu rr en t, I

sub

(A )

Line : Model

Fig. 5.11.2: Analytical solution of the subthreshold current for junctionless tri-material surrounding-gate gate-stack MOSFETs compared with 3D numerical simulation results with the effective gate oxide thickness as a varied parameter.

0 0.2 0.4 0.6

Su b thr es h o ld Cu rr en t, I

sub

(A )

Line : Model

Fig. 5.11.3: Analytical solution of the subthreshold current for junctionless tri-material surrounding-gate gate-stack MOSFETs compared with 3D numerical simulation results with the silicon film thickness as a varied parameter.

0 0.2 0.4 0.6 Gate Bias, V

_gs

(V)

1x10

^-16

1x10

^-15

1x10

^-14

1x10

^-13

1x10

^-12

1x10

^-11

1x10

^-10

1x10

^-9

1x10

^-8

1x10

^-7

1x10

^-6

1x10

^-5

Su b thr es h o ld Cu rr en t, I

sub

(A )

Line : Model Symbol : ISE -/- : L_g = 60 nm -,- : Lg = 90 nm -&- : L_g = 120 nm

L₁:L₂:L₃ = 1:1:1 t_oxeff = 2 nm t_si = 20 nm N_d = 1x10¹⁸ cm^-3 F_M1 = 4.8 eV F_M2 = 4.5 eV F_M3 = 4.2 eV

Fig. 5.11.4: Analytical solution of the subthreshold current for junctionless tri-material surrounding-gate gate-stack MOSFETs compared with 3D numerical simulation results with the channel length as a varied parameter.

在文檔中 参閘極與環繞閘極金氧半場效電晶體含氧化層介面缺陷電荷與絕緣層堆疊結構之次臨界行為研究 (頁 137-151)