Results and Discussion - A NEW QUASI-THREE-DIMENSIONAL SUBTHRESHOLD CURRENT

Chapter 2 A NEW QUASI-THREE-DIMENSIONAL SUBTHRESHOLD CURRENT

2.4 Results and Discussion

We used the 3D device simulator "DESSIS" [28] to validate the proposed model.

With the fixed positive/negative trapped charges, Fig. 2.4.1 plots ITSUBD versus normalized damaged zone Ld/Lg for different silicon film thicknesses. Increased the Ld/Lg can further enhance ITSUBD for both positive and negative trapped charges. A thick silicon film of tsi=40 nm is desirable for reducing the ITSUBD caused by the both positive and negative trapped charges. Fig. 2.4.2 shows ITSUBD with Ld/Lg for different gate oxide thicknesses. Irrespective of the polarities for the trapped charges, tox=1 nm induces a smaller ITSUBD than tox=2 nm and 3 nm. Although a thin gate oxide is needed to make the device suffer less ITSUBD, it may initiate the oxide leakage current due to the tunneling effects, which will cause the static power consumption. The trade-off regarding how to reduce ITSUBD without inducing the gate leakage current caused by the tunneling effects should be taken into account as the thin gate device is applied for memory circuits. Fig. 2.4.3 plots ITSUBD versus normalized damaged zone for different stressed lengths near the drain side. The ITSUBD is increased when Ls is increased, which implies that for the fixed channel length, the device will suffer severe ITSUBD when the damaged zone Ld keeps away from the drain side corresponding to the increased Ls. Fig. 2.4.4 plots ITSUBD versus normalized damaged zone for different channel lengths. Although the channel device shows worse immunity to short-channel effects (SCEs), it suffers less ITSUBD caused by the ITCEs than the long-channel device when the normalized damaged zone is increased. On the contrary, the long-channel device suffers more ITSUBD caused by ITCEs than the short-channel device. Fig. 2.4.5 plots ITSUBD as a function of Ld/Lg for different drain voltages Vds. As opposed to SCEs, the larger Vds can reduce more ITCEs that improve the ITSUBD more efficiently than the smaller Vds. Although the enhanced SCEs in Fig. 2.4.1, Fig.

2.4.4, and Fig. 2.4.5 can alleviate ITSUBD more efficiently, the physical insight into the device physics is that when the SCEs are enhanced by the choice of device dimensions and drain voltage, the virtual cathode (i.e., the location of the leakiest path) will move toward the source side [29][30], which hence increases the distance between the damaged zone and the virtual cathode and the impact of the interface trapped charges (i.e., ITCEs) on the short-channel subthreshold current degradation (i.e., ITSUBD) can be expected to be reduced due to the enlarged distance from the virtual cathode to damaged zone. Fig. 2.4.6 plots ITSUBD versus normalized damaged zone for different trapped charge densities. The more trapped charge density the device has, the more ITSUBD the device will encounter. Fig. 2.4.7 plots subthreshold current roll-up versus the channel length for both damaged and fresh devices. The subthreshold current roll-up (SUBRUP) is defined by the difference between the long-channel and short-channel devices for their subthreshold currents in logarithm scales. (i.e., SUBRUP =Log[Ids,short ]-Log[Ids,long]). As the channel length is reduced, the damaged device with negative trapped charges suffers less short-channel effects (SCEs) and has a smaller SUBRUP than the fresh device. In contrast to the negative trapped charges, the positive trapped charges can enhance SCEs and cause the damaged device more SUBRUP than the fresh device when the channel length is further decreased. The ITSUBD versus Ld/Lg for the different device structures, including JLDG, JLTG, and JLQG transistors, is demonstrated in Fig. 2.4.8. It shows that the JLDG device can resist ITSUBD more efficiently than both JLQG and JLTG devices when Ld/Lg is increased. As opposed to SCEs, JLQG device rather than JLDG device will suffer severe ITSUBD induced by ITCEs. Being similar to Fig. 2.4.1, Fig. 2.4.4, and Fig. 2.4.5, since JLDG FET suffers more SCEs than both JLQG and JLTG FETs, it will be the best among the three FETs in resisting ITCEs that brings about the severe ITSUBD. Although the quantum mechanics effects (QMEs) are not included in the present model, the ITSUBD in the QM case

should be identical to it in the classical case because both damaged and fresh device experience the same QMEs.

-4 -2 0 2 4

IT S U BD (A)

0 0.2 0.4 0.6 0.8 1

Normalized Damaged Zone, L

/L

Solid Line:Damaged device with +Nf Dash Line:Damaged device with -Nf Line : Model

Solid Line:Damaged device with +Nf Dash Line:Damaged device with -Nf Line : Model

Fig. 2.4.6: ITSUBD versus normalized damaged zone for different uniform interface trapped charge density.

-4

Channel Length (nm), L

Line : Model Symbol : ISE

-&- : Damaged Device with +Nf

-,- : Fresh Device

Fig. 2.4.7: Subrup versus gate length for both fresh and damaged devices.

-8 -4 0 4 8

IT S U BD (A)

0 0.2 0.4 0.6 0.8 1

Normalized Damaged Zone, L

/L

Solid Line:Damaged device with +Nf Dash Line:Damaged device with -Nf Line : Model

Symbol : ISE

-_&- : Double-Gate

-,- : Triple-Gate -2- : Quadruple-Gate

V_ds = 0.05 V V_gs = 0.2 V t_ox = 3 nm t_si = 30 nm L_g = 50 nm L_s = 0 nm N_f = 1x10¹² cm^-2 N_d = 1x10¹⁸ cm^-3

Fig. 2.4.8: ITSUBD versus normalized damaged zone for different device structures, including JLDG, JLTG, and JLQG MOSFETs.

Chapter 3 TWO-DIMENSIONAL SUBTHRESHOLD BEHAVIOR MODEL FOR

SURROUNDING-GATE MOSFETs WITH INTERFACE TRAPPED CHARGES

3.1 Quasi-2D Subthreshold Behavior Model for

Surrounding-Gate MOSFETs with Interface Trapped Charges

3.1.1 Introduction

ITRS has revealed that the implantations of non-classical CMOS structures are needed to overcome the difficult challenges when the semiconductor technology node is below 16 nm [1]. It also indicates that the multiple-gate (MG) MOSFETs with the strong field confinement, prominent volume conduction, and high packing density can be the promising candidates for the future CMOS application. Several literatures have reported that the novel structures for the surrounding-gate (SRG) MOSFETs with the high performance and scalability can be used for the memory DRAM cell [14]. To utilize this device for the memory cell application, it is mandatory to develop a feasible model. Although a numerous of literatures have modeled the drain current for the MG devices [31], [32], there are no investigations on the subthreshold current model for the surrounding-gate (SRG) MOSFETs with the interface trapped charges. In this letter, by accounting for the effects of interface trapped charges on the flatband voltage, we propose a compact subthreshold current model for the SRG MOSFETs with the

interface trapped charges based on the scaling equation and drift-diffusion approach.

The proposed model explicitly illustrates how the interface trapped charges with different polarities, damaged zone lengths, gate oxide, and silicon body thicknesses affect the subthreshold current degradation.

Hot-carrier effects that bring about the accumulated interface trapped charges will degrade the device/circuit performance [33], [3]. A number of literature works have modeled the hot-carrier-induced threshold voltage of planar and double-gate MOSFETs in the past decade [4], [5]. However, the wrong eigenvalue of k for the potential developed by the double-gate model [4] could mislead the device physics. Surrounding-gate MOSFETs showing better scaling length are more promising than both planar and double-gate MOSFETs for future VLSI circuits. Until now, there have been few papers investigating the threshold-voltage model of surrounding-gate MOSFETs with trapped charges [34]. In this chapter, by considering the effects of equivalent oxide charges on flatband voltage [27], a compact analytical threshold-voltage model for surrounding-gate MOSFETs with interface trapped charges is developed. The proposed model is verified by numerical simulation [28] and explicitly illustrates how trapped-charge density with different polarities, damaged zone, oxide thickness, and diameter of silicon body affect the threshold-voltage behavior. It not only offers physical insight into hot-carrier effects on threshold voltage but also provides basic design guidance for charge-trapped memory devices.

3.1.2 Model Description

Fig. 3.1.1 shows the 3D device structure to derive the model. With various interface trapped-charge distributions, the channel regions can be divided into three zones, region 1, 2, and 3 signify the low-field region near the source, the high-field region with damage, and the high-field region without damage, respectively.

Fig. 3.1.1: Typical schematic of the 3D SRG device structure. Regions 1, 3, and 2 are defined by region 1: fresh region at the interface of Si/SiO2 near the source side when 0

≦z≦Lg-Ld-Ls, region 2: damaged region at the interface of Si/SiO2 when Lg-Ld-Ls≦z

≦Lg- Ls, and region 3: fresh region at the interface of Si/SiO2 near the drain side when Lg-Ls≦z≦Lg. Lg is the channel length, Ld is the damaged zone, Ls is the fresh zone near the drain side, and Lg-Ld-Ls is the fresh zone near the source side.

3.1.3 Threshold Voltage Model Derivation

With various interface trapped-charge distributions, the channel regions can be divided into three zones. By considering the central conduction mode and using the parabolic approach to solve for the 2D Poisson equation in each of the three zones, the potential along the vertical channel direction can be assumed [37] Φi(r, z) = C1,i(z) + C2,i(z)r + C3,i(z)r² (i = 1, 2, and 3 signify the low-field region near the source, the high-field region with damage, and the high-high-field region without damage, respectively) to satisfy the following conditions:

1, , effective capacitance per unit area [37], and Vfb,1 = Vfb,3 is the flatband voltage in the undamaged regions. In the damaged region, due to the effect of equivalent oxide charges on flatband voltage [27], we obtain

,2 ,1 0 ,1

Where ρ(x) is the localized oxide charge density assumed to be zero for simplicity and Qit = qNf is the uniform interface charge sheet density. With the determined C1,i, C2,i, and C3,i from (3.1.1) and by setting r = 0 for the central conduction channel, the central potential Φc,i(z) should satisfy

Where the subscript of i =1, 3 denotes the fresh region and i=2 denotes the damaged region, Cox is effective oxide capacitance per unit area, Vgs is the gate bias, λSRG and φC,i are the scaling length and long-channel central potential, respectively, and Vfb,1=Vfb,3 is the flat-band voltage in the fresh region. By solving for the ordinary differential equation, the general solution of (3.1.3) can be obtained as

, ( ) ^SRG ^SRG ,

z z

C i z a ei ^λ b ei ⁻^λ φC i

Φ = + + (3.1.6)

According to the continuity of both electric field and potential at the boundary conditions at damaged/fresh regions, source/silicon and drain/silicon junctions, ai and bi

in (3.1.6) can be obtained as

3 ,1 central potential in both fresh and damaged regions, respectively.

Therefore, the minimum central potential can be expressed as

, ,min 2 ,

( )

Vbi is the built-in voltage at the source/channel and drain/channel junctions and Vds

is the drain voltage.

The largest value of VTH,i in (3.1.14) will dominate the threshold voltage behavior.

3.1.4 Threshold Voltage Model Result

The 3D device simulator “DESSIS” is used to verify the proposed model. The threshold voltage is read when the electron concentration at the position of the minimum central potential is equal to the bulk doping density. For the fixed positive/negative interface sheet charge density, Fig. 3.1.2 shows the dependence of threshold-voltage degradation on the normalized damaged zone for different diameters of silicon body. The increased damaged zone can further degrade the threshold voltage by reflecting the effects of negative/positive interface trapped charges on the weakening/strengthening DIBL from the lateral electric field of the drain side. This interface-trapped-charge-induced threshold-voltage degradation is called “ITTVD.” For positive interface charges, the small diameter of silicon body of tsi = 10 nm will suffer less ITTVD in comparison to the large diameter of tsi = 30 nm when Ld is increased.

However, the small diameter of tsi = 10 nm with negative interface charges will not suffer more ITTVD than the large diameter of tsi = 30 nm until the normalized damaged zone of Ld/Lg is shrunk approximately below 0.55. Fig. 3.1.3 shows the variation of threshold-voltage degradation with the normalized damaged zone for different oxide thicknesses. Positive/negative interface charges with large damaged zone will bring about great threshold-voltage degradation, particularly for thick oxide thickness. To make the device suffer less ITTVD, not only the thin gate oxide should be accounted for but also the small damaged zone must be desired for the device.

Fig. 3.1.4 shows the dependence of threshold-voltage roll-off on channel length for both damaged and fresh devices. The device with negative charges suffers less SCEs than the fresh device due to screening DIBL, which hence reduces the threshold-voltage roll-off. On the other hand, positive charges can enhance DIBL that will induce severe

ITTVD and cause the damaged device more threshold-voltage roll-off than the fresh device.

0 0.2 0.4 0.6 0.8 1

Normalized Damaged Zone, L

/L

-0.16

-0.08 0 0.08 0.16

IT TVD ( V)

Solid Line :Damaged device with +Nf Dash Line :Damaged device with -Nf Line : Model

Symbol : ISE

-2- : t_si = 10 nm

-_{,- : t}_si = 20 nm -&- : t_si = 30 nm

V_ds = 0.05 V L_s = 0 nm L_g = 50 nm t_ox = 2 nm

N_d = 1x10²⁰ cm^-3 N_a = 1x10¹⁶ cm^-3 N_f = 1x10¹² cm^-2

Fig. 3.1.2: Threshold-voltage degradation versus normalized damaged zone for different diameters of silicon body

0 0.2 0.4 0.6 0.8 1 Normalized Damaged Zone, L

/L

-0.2

Solid Line:Damaged device with +Nf Dash Line: Damaged device with -Nf Line : Model

Fig. 3.1.3: Threshold-voltage degradation versus normalized damaged zone for different oxide thicknesses.

Th re sh old V o lt age R oll- o ff (V )

-&-

Damaged device with +Nf

Fig. 3.1.4: Threshold-voltage roll-off versus channel length for both fresh and damaged devices.

3.1.5 Subthreshold Current Model Derivation

For various trapped charge distributions, the channel can be divided into three regions as shown in Fig. 3.1.1. In the subthreshold regime, the channel central potential should satisfy the following scaling equation [35]:

Where the subscript of i =1, 3 denotes the fresh region and i=2 denotes the damaged region, Cox is effective oxide capacitance per unit area, Vgs is the gate bias, λSRG and φC,i are the scaling length and long-channel central potential, respectively, and Vfb,1=Vfb,3 is the flat-band voltage in the fresh region. Due to the effect of equivalent oxide charges on the flat-band voltage, the flat-band voltage in the damaged region can be expressed by [27]:

,2 ,1 ,1

Where Qit= qNf is the interface trapped charge density that is assumed uniform for simplicity. The general solution of (3.1.27) is

, ( )= ^SRG ^SRG ,

z z

C i z a ei ^λ b ei ⁻^λ φC i

Φ + + (3.1.31)

According to the continuity of both electric field and potential at the boundary conditions at damaged/fresh regions, source/silicon and drain/silicon junctions, ai and bi

in (3.1.31) can be obtained as

1 1 2 central potential in both fresh and damaged regions, respectively.

Therefore, the minimum central potential in (3.1.31) can be expressed as

, ,min 2 ,

C i a bi i φC i

Φ = + (3.1.38)

Based on the parabolic potential approach, the channel potential Φi that comprises the surface potential ΦS,i and the central potential ΦC,i can be written as [36]

, 2 , , 2

According to (3.1.39), the minimum channel potential can be composed of the minimum central potential and minimum surface potential. This yields

,min( ) , ,min ^ox2( , , ,min) 2

i C i gs fb i S i

si si

r C V V r

Φ = Φ +C t − − Φ (3.1.40)

By substituting r = tsi/2 into (3.1.40), the minimum surface potential can be expressed by the minimum central potential. This leads to

, ,min [ , ,min ( ,)] (1 )

with the drift-diffusion approach, the charge-trapped subthreshold current density for SRG MOSFETs can be expressed by

,min

Where ni,min(r, z) is the electron density at the virtual cathode point, Na is the bulk doping density and Φn(z) is the electron quasi-Fermi potential. By integrating (3.1.42) in r and θ, in which (3.1.40) and (3.1.43) are used for the integration, the subthreshold current along z-direction can be determined as

2 2

→ dΦ) and by integrating (3.1.44) in z-direction, the subthreshold current can be obtained as (3.1.45). Finally, the smallest ΦC,i,min and ΦS,i,min in (3.1.38) and (3.1.41) will dominate the interface–trapped-charge-induced subthreshold current for SRG MOSFETs.

3.1.6 Subthreshold Current Model Result

The 3D device simulator “DESSIS” [28] is used to validate the proposed model.

Interface-Trapped-Charges-Induced Subthreshold Current Degradation is the called ITSUBD that is defined by the difference between the fresh and damaged devices for their subthreshold currents in logarithm scales (i.e., ITSUBD = log[Ids,damaged] − log[Ids,fresh]). With the fixed positive/negative interface trapped charges, Fig. 3.1.5 plots ITSUBD versus normalized damaged zone Ld/Lg for different silicon film thicknesses.

Increased the Ld/Lg can further enhance ITSUBD for the positive and negative trapped charges. A thick silicon film of tsi = 40 nm is desirable for reducing the ITSUBD caused by the negative trapped charges. On the contrary, a thin silicon film, such as tsi = 20 nm is preferred to suppress ITSUBD caused by the positive trapped charges. Fig. 3.1.6 shows ITSUBD with Ld/Lg for different gate oxide thicknesses. Irrespective of the polarities for the trapped charges, tox = 3 nm induces a smaller ITSUBD than tox = 4 nm and 5 nm. Although the thin gate oxide is needed to make the device suffer less ITSUBD, it may initiate the oxide leakage current due to quantum mechanical effects (QMEs), which will cause the static power consumption. The trade-off about how to reduce ITSUBD without inducing the gate leakage current caused by QMEs should be taken into account as the thin gate device is applied for memory circuits. Fig. 3.1.7 plots subthreshold current roll-up versus the gate length for damaged and fresh devices. The subthreshold current roll-up (SUBRUP) is defined by the difference between the long-channel and short-long-channel devices for their subthreshold currents in logarithm scales.

(i.e., SUBRUP = log[Ids,short] − log[Ids,long]). As the gate length is reduced, the damaged device with negative trapped charges suffers less short-channel effects (SCEs) and induces a smaller SUBRUP than the fresh device. In contrast to the negative trapped charges, the positive trapped charges can enhance SCEs and cause the damaged device

more SUBRUP than the fresh device when the gate length is further decreased.

0 0.2 0.4 0.6 0.8 1

Normalized Damaged Zone, L

/L

-6

-4 -2 0 2 4 6

IT S U BD (A)

V_ds=0.05 V V_gs=0.5 V t_ox= 3 nm L_g= 100 nm L_s= 0 nm

Line : Model Symbol : ISE Solid Line: Damaged device with +Nf

Dash Line : Damaged device with -Nf -2- : t_si= 20 nm

-,- : t_si= 30 nm -&- : t_si= 40 nm

N_a = 1x10¹⁶ cm^-3 N_d = 1x10²⁰ cm^-3 N_f = 1x10¹² cm^-3

Fig. 3.1.5: ITSUBD versus normalized damaged zone for different silicon body thicknesses.

0 0.2 0.4 0.6 0.8 1 Normalized Damaged Zone, L

/L

-6

Solid Line: Damaged device with +Nf Dash Line: Damaged device with -Nf -2- : t_ox= 3 nm

Fig. 3.1.6: ITSUBD versus normalized damaged zone for different gate oxide thicknesses.

-&-:Damaged device with +Nf

-,-

:

Fresh Device

-2-:Damaged device with -Nf

Fig. 3.1.7: SUBRUP versus gate length for the fresh and damaged devices.

3.2 Full-2D Subthreshold Behavior Model for

Surrounding-Gate MOSFETs with Interface Trapped Charges

3.2.1 Model Description

Fig. 3.2.1 shows the 3D device structure to derive the model. With various interface trapped-charge distributions, the channel regions can be divided into three zones, region 1, 2, and 3 signify the low-field region near the source, the high-field region with damage, and the high-field region without damage, respectively.

Fig. 3.2.1: Typical schematic of the 3D SRG device structure. Regions 1, 3, and 2 are defined by region 1: fresh region at the interface of Si/SiO2 near the source side when 0

≦z≦Lg-Ld-Ls, region 2: damaged region at the interface of Si/SiO2 when Lg-Ld-Ls≦z

3.2.2 Model Derivation

We assume that the impurity density is uniform in the channel region. The channel potential distribution is expressed by ( , )ψ_i r z . According to the Poisson equation, the channel potential distribution in the cylindrical is given by:

2 2

Where Na is the uniform doping concentration of the silicon film, tox is the gate oxide thickness, tsi is the silicon film thickness, Lg is the device channel length, the z-axis is parallel to the channel length, the subscript of i = 1, 3 denotes the fresh region and i = 2 denotes the damaged region, respectively. By using the superposition

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