Potential Contour

Fig. 4.2.6 and Fig. 4.2.7 show the analytical potential contours and simulated data by the three-dimensional device simulator with Ld = 0 nm and Ld = 25 nm with positive trapped charge. A close agreement between them is observed, which further verifies the accuracy of our model. It is seen that the potential contours under the gate bend vertically into the channel, which implies that the electric fields from the gate will penetrate the channel and control the threshold behavior [41]. Among Fig. 4.2.6 and Fig. 4.2.7, it can be seen that with the positive trapped charge, the potential contours of the undamaged region have the tendency to bend vertically, which implies that the electric fields from the undamaged region can easily penetrate into the channel and control the threshold behavior. In contrast, the potential contours of the damaged region are prone to bent horizontally. It indicates that the most of the lateral electrical field induced by drain voltage is completely absorbed in the damaged region, resulting in the effective suppression to DIBL.[42]

0 10 20 30 40 50 Channel Position, z (nm)

-10 -5 0 5 10

V ertical P osition, r (n m )

: Model

Fig. 4.2.6: 2D electrostatic potential contours of channel along channel. The simulated device parameters are Lg=50 nm, Ld=0 nm, tox = 2 nm, tsi = 20 nm, Vgs = 0.5 V, and Vds

= 0 V.

0 10 20 30 40 50

Channel Position, z (nm) -10

-5 0 5 10

V ertical P osition, r (n m )

: Model

Fig. 4.2.7: 2D electrostatic potential contours of channel along channel. The simulated device parameters are Lg=50 nm, Ld=25 nm, tox = 2 nm, tsi = 20 nm, Vgs = 0.5 V, and Vds

= 0 V.

4.2.7 Threshold Voltage Model

The threshold voltage can be considered as the gate bias in which bulk conduction starts to occur. This condition is satisfied when there is a point at the center of the channel that is not depleted. As the source of the device is directly connected to the ground and as there are no junctions, the potential at this point can be considered as zero (ψ_i,min( ) 0r = ).

In order to solve analytical threshold voltage, we need to rewrite coefficients as a linear equation related to VGS. From eq.(4.2.21), eq.(4.2.22) and eq.(4.2.30 ~ 4.2.35), we get

2

By using eq.(4.2.51) ~ eq.(4.2.56), we can get the minimum potential as a linear equation related to gate bias VGS.

( )

1,_i 4 _{i i} 1

T = α η − (4.2.71)

2,_i 2( _{i i i i}) _i

T = α δ β η+ − (4.2.72) k

2

3,_i 4 _{i i i}

T = β δ −k (4.2.73)

2

, 4 16

d d

i FB i si si

ox si

qN qN

k V t t

C ε

= − + +

′ (4.2.74)

From eq.(4.2.69), ψ_i,min = , and solving for V0 GS, the threshold voltage can be achieved. Due to reducing the complicated calculation and its rapid decay of Fourier series, choose the first term can dominate the whole series. Thus

2

2, 2, 1, 3,

,

1,

i i i i

TH i

i

T T T T

V T

− + −

= (4.2.75)

The largest VTH,i in above equation will dominate the threshold voltage.

4.2.8 Threshold Voltage Model Result

Fig. 4.2.8 shows how the threshold voltage degradation is affected by the normalized damaged zone for the different silicon thicknesses. The increased damaged zone can further degrade the threshold voltage by reflecting the effects of the localized negative/positive trapped charges on the threshold voltage degradation. This interface trapped charge induced threshold voltage degradation is called “ITTVD”. For the positive trapped charges, large thickness of tsi=30 nm will suffer more ITTVD than the small one of tsi=10 nm when Ld is increased. However, the large thickness of tsi=30 nm with negative trapped charges will suffer less ITTVD than the small thickness of tsi=10nm until the normalized damaged zone of Ld/Lg is increasing beyond 0.7. Fig.

4.2.9 shows the dependence of threshold voltage degradation on the normalized damaged zone for different gate oxide thicknesses. The interface trapped charges with large normalized damaged zone will cause great threshold voltage degradation, especially for the thick oxide thickness. To reduce ITTVD, not only the thin gate oxide should be accounted for, but also the small damaged zone must be desired for the device. Fig. 4.2.10 plots ITTVD versus normalized damaged zone for different trapped charge densities. The more trapped charge density the device has, the more ITTVD the device will encounter. Fig. 4.2.11 plots ITTVD versus normalized damaged zone for different channel lengths. For the positive trapped charges, long channel of Lg=70 nm will suffer less ITTVD than the short one of Lg=30 nm when Ld is increased. However, the long channel of Lg=70 nm with negative trapped charges will suffer more ITTVD than the short channel of Lg=30 nm until the normalized damaged zone of Ld/Lg is increasing beyond 0.85. Fig. 4.2.12 depicts the dependence of the threshold voltage roll-off on the gate length for both damaged and fresh devices. The ITTVD may be coupled with the DIBL. Since the ITTVD caused by the negative trapped charges has an

opposed effect to DIBL, the threshold voltage roll-off for the negative trapped-charge device will be decreased and become less than that for the fresh device when the channel length is decreased. On the contrary, the ITTVD caused by the positive trapped charges takes the same effect as DIBL and the threshold voltage roll-off for the positive trapped-charge device will be enhanced and become more than that of the fresh device.

Although the negative trapped charge can alleviate DIBL, it will bring about the large threshold voltage. This could be an obstacle for the low-voltage circuit application.

Otherwise, 3D model is required to simulate the junctionless surrounding-gate device accurately. With the better control of SCEs than the planar MOSFETs, the advanced non-planar multi-gate (MG) MOSFETs such as the double-gate (DG), tri-gate (TG), and junctionless surrounding-gate (SRG) MOSFETs are the more attractive devices for the nanometer MOSFET application.

It should be pointed out that although the quantum mechanical effects (QM) is not accounted for in the work, it has been derived in the previous literatures [43] that QM will pull up the threshold voltage since the quantum mechanical channel potential barrier is larger than classical channel potential barrier, which will increase the gate voltage for inverting the channel. It can be concluded that the threshold voltage in Fig.

4.2.12 will shift upward in parallel by considering QM.

0 0.2 0.4 0.6 0.8 1 Normalized Damaged Zone, L

_d

/L

_g

-0.18

Solid Line :Damaged device with +Nf Dash Line :Damaged device with -Nf Line : Model

Fig. 4.2.8: ITTVD versus the normalized damaged zone for different silicon film thicknesses.

0 0.2 0.4 0.6 0.8 1

Normalized Damaged Zone, L

_d

/L

_g

-0.18

Solid Line:Damaged device with +Nf Dash Line: Damaged device with -Nf Line : Model

Fig. 4.2.9: ITTVD versus the normalized damaged zone for different oxide thicknesses.

0 0.2 0.4 0.6 0.8 1 Normalized Damaged Zone, L

_d

/L

_g

-0.22

Solid Line :Damaged device with +Nf Dash Line :Damaged device with -Nf Line : Model

Fig. 4.2.10: ITTVD versus normalized damaged zone for different uniform interface trapped charge density.

0 0.2 0.4 0.6 0.8 1

Normalized Damaged Zone, L

_d

/L

_g

-0.18

Solid Line :Damaged device with +Nf Dash Line :Damaged device with -Nf Line : Model

Fig. 4.2.11: ITTVD versus normalized damaged zone for different channel lengths.

20 30 40 50 60 70 Channel Length, L

_g

(nm)

-0.16 -0.12 -0.08 -0.04 0 0.04

Thre sh old Voltag e Roll -o ff (V)

-&-

Damaged device with +Nf

-,-

Fresh Device

-2-

Damaged device with -Nf

V_ds = 0.05 V

t_si = 30 nm t_ox = 3 nm L_d =10 nm L_s = 0 nm

N_d = 1x10¹⁸cm^-3 N_f = 1x10¹²cm^-2 Line : Model

Symbol : ISE

Fig. 4.2.12: Threshold-voltage roll-off versus channel length for both fresh and damaged devices.

4.2.9 Subthreshold Current Model

Knowing the minimum channel potential solution of (4.2.50), we can proceed to derive the subthreshold current. Since the current density for the junctionless surrounding-gate MOSFET flows predominantly in the z direction (from source to drain), the electron quasi-Fermi potential is essentially constant in the r-direction and is only function of z. By using the drift-diffusion approach, the current density (both drift and diffusion) together with the electron carrier density at the virtual cathode point can be written as

where ni is the intrinsic carrier density. By integrating (4.2.76) in z and directions, the subthreshold current for the surrounding-gate MOSFET can be obtained as

,min( ) ( )

Since the current is constant along the channel direction of z, integration of (4.2.78) with respect to z from 0 to yields Lg. The general subthreshold current can be expressed as

Because it is too complicated to express and calculate the integral re^Φi,min/VT in eq.(4.2.79), a numerical solution is used to simplify the exponential forms. To obtain the

analytical expression, we take advantage of trapezoidal integration rule. Therefore, the double integrals in eq.(4.2.79) can be rewritten as

,min( ) 2 ,

1

(1 ) ,1

si DS i

T T

nt

V m m

V V

T d si

sub i

g n

V q N t

I e re m

mL

π μ ⁻ ψ

=

= −

∑

≤ ≤ ∞ ^(4.2.80)

Where m is the partition numbers in the interval of [0,tsi/2]. From eq.(4.2.79) and eq.(4.2.80) the analytical subthreshold current model can be theoretically achieved.

4.2.10 Subthreshold Current Model Result

We used the 3D device simulator "DESSIS" [28] to validate the proposed model.

With the fixed positive/negative trapped charges, Fig. 4.2.13 plots ITSUBD versus normalized damaged zone Ld/Lg for different silicon film thicknesses. Increased the Ld/Lg can further enhance ITSUBD for both positive and negative trapped charges. A thick silicon film of tsi=30 nm is desirable for reducing the ITSUBD caused by the both positive and negative trapped charges. Fig. 4.2.14 shows ITSUBD with Ld/Lg for different gate oxide thicknesses. Irrespective of the polarities for the trapped charges, tox=1 nm induces a smaller ITSUBD than tox=2 nm and 3 nm. Although a thin gate oxide is needed to make the device suffer less ITSUBD, it may initiate the oxide leakage current due to the tunneling effects, which will cause the static power consumption. The trade-off regarding how to reduce ITSUBD without inducing the gate leakage current caused by the tunneling effects should be taken into account as the thin gate device is applied for memory circuits. Fig. 4.2.15 plots ITSUBD versus normalized damaged zone for different stressed lengths near the drain side. The ITSUBD is increased when Ls is increased, which implies that for the fixed channel length, the device will suffer severe ITSUBD when the damaged zone Ld keeps away from the drain side corresponding to the increased Ls. Fig. 4.2.16 plots ITSUBD versus normalized damaged zone for different channel lengths. Although the short-channel device shows worse immunity to short-channel effects (SCEs), it suffers less ITSUBD caused by the ITCEs than the long-channel device when the normalized damaged zone is increased.

On the contrary, the long-channel device suffers more ITSUBD caused by ITCEs than the short-channel device. Fig. 4.2.17 plots ITSUBD as a function of Ld/Lg for different drain voltages Vds. As opposed to SCEs, the larger Vds can reduce more ITCEs that improve the ITSUBD more efficiently than the smaller Vds. Although the enhanced

SCEs in Fig. 4.2.13, Fig. 4.2.16, and Fig. 4.2.17 can alleviate ITSUBD more efficiently, the physical insight into the device physics is that when the SCEs are enhanced by the choice of device dimensions and drain voltage, the virtual cathode (i.e., the location of the leakiest path) will move toward the source side [29][30], which hence increases the distance between the damaged zone and the virtual cathode and the impact of the interface trapped charges (i.e., ITCEs) on the short-channel subthreshold current degradation (i.e., ITSUBD) can be expected to be reduced due to the enlarged distance from the virtual cathode to damaged zone. Fig. 4.2.18 plots ITSUBD versus normalized damaged zone for different trapped charge densities. The more trapped charge density the device has, the more ITSUBD the device will encounter. Fig. 4.2.19 plots subthreshold current roll-up versus the channel length for both damaged and fresh devices. The subthreshold current roll-up (SUBRUP) is defined by the difference between the long-channel and short-channel devices for their subthreshold currents in logarithm scales. (i.e., SUBRUP =log[Ids,short]-log[Ids,long]). As the channel length is reduced, the damaged device with negative trapped charges suffers less short-channel effects (SCEs) and has a smaller SUBRUP than the fresh device. In contrast to the negative trapped charges, the positive trapped charges can enhance SCEs and cause the damaged device more SUBRUP than the fresh device when the channel length is further decreased. Although the quantum mechanics effects (QMEs) are not included in the present model, the ITSUBD in the QM case should be identical to it in the classical case because both damaged and fresh device experience the same QMEs.

-4

Normalized Damaged Zone, L

_d

/L

_g

Solid Line:Damaged device with +Nf Dash Line:Damaged device with -Nf Line : Model

Fig. 4.2.13: ITSUBD versus normalized damaged zone for different silicon body thicknesses.

Normalized Damaged Zone, L

_d

/L

_g

Solid Line:Damaged device with +Nf Dash Line:Damaged device with -Nf Line : Model

Fig. 4.2.14: ITSUBD versus normalized damaged zone for different gate oxide thicknesses.

-4

Normalized Damaged Zone, L

_d

/L

_g

Solid Line:Damaged device with +Nf Dash Line:Damaged device with -Nf Line : Model

Fig. 4.2.15: ITSUBD versus normalized damaged zone for different stressed near the drain side Ls.

Normalized Damaged Zone, L

_d

/L

_g

Solid Line:Damaged device with +Nf Dash Line:Damaged device with -Nf Line : Model

Fig. 4.2.16: ITSUBD versus normalized damaged zone for different channel lengths.

-4

Normalized Damaged Zone, L

_d

/L

_g

Solid Line:Damaged device with +Nf Dash Line:Damaged device with -Nf Line : Model

Fig. 4.2.17: ITSUBD versus normalized damaged zone for different drain bias.

-8

Normalized Damaged Zone, L

_d

/L

_g

Solid Line:Damaged device with +Nf Dash Line:Damaged device with -Nf Line : Model

Fig. 4.2.18: ITSUBD versus normalized damaged zone for different uniform interface trapped charge density.

-2 0 2 4 6 8

SU B R UP ( A )

20 40 60 80 100

Channel Length, L

_g

(nm)

Line : Model Symbol : ISE

-&- : Damaged Device with +Nf

-,- : Fresh Device

-_2- : Damaged Device with -Nf

N_d = 1x10¹⁸ cm^-3 N_f = 1x10¹² cm^-2 t_ox = 2 nm

t_si = 20 nm L_s = 10 nm L_d = 10 nm V_ds = 0.05 V V_gs = 0.5 V

Fig. 4.2.19: Subrup versus gate length for both fresh and damaged devices.

Chapter 5

TWO DIMENSIONAL SUBTHRESHOLD BEHAVIOR MODEL FOR JUNCTIONLESS

TRIMATERIAL GATE-STACK SURROUNDING-GATE MOSFETs

(JLTMGSRG)

5.1 Introduction

With the advancement of the gate material engineering, dual-material gate (DMG) MOSFETs has been investigated and expected to suppress the short channel effects (SCEs) and enhance the carrier transport efficiency[44][45]. The DMG MOSFET will induce the step potential at the interface between the different gate materials and make a peak electric field in the channel region that improves the carrier transit speed and increases the device driving capability. Owing to the screen effects of DMG MOSFET, the high electric field near the drain side can be effectively reduced, which suppresses the hot carrier effects (HCEs) and reduces the substrate current leakage. During the last decade, high-k dielectrics have been studied as an alternative to SiO2 based gate dielectric to reduce the gate leakage current. The use of high-k materials in the oxide region can effectively reduce gate leakage current with continuous thinning of gate oxide layer [7]. The gate-stack structure with a gate oxide of SiO2 as an interfacial buffer between bulk silicon and high-k dielectrics can screen the effect of phonon scattering and improve the carrier mobility [8]. The straddle-gate structure with three materials as gate electrode was proposed by S. Tiwari et al. [9] to reduce source-to-drain leakage current due to the threshold voltage of the side gates that is smaller than that of

the main gate. Co-operating the advantage of gate-stack with straddle-gate structure, R.S. Gupta et al. [10] suggested the tri-material gate-stack (TRIMGAS) MOSFET. They also developed the analytic model of the short-channel TRIMGAS MOSFET on the based of the quasi-two-dimensional (quasi-2D) potential approach. In order to extend the scalability of MOSFET technology, supplant the very shallow source/drain, and overcome the doping techniques, a new device structure that is so-called as the junctionless tri-material gate-stack surrounding-gate (JLTMGSRG) MOSFET as shown in Fig. 5.1.1. The inherent drawback of the large errors in predicting the potential profile near the source/drain [46] makes quasi-2D potential approach inaccurate to portray the two-dimensional (2D) potential contours which are essential for demonstrating the electric characteristics of the devices. To precisely analyze the junctionless tri-material gate-stack surrounding-gate MOSFETs when it is applied for the digital circuits, it is mandatory to develop the exactly 2D behavior model. In this work, on the basis of the exact solution of 2D Poisson equation, we successfully developed a new compact analytical model comprising 2D potential, threshold voltage and subthreshold current.

The calculated results of the model match well with those simulated of the device simulator DESSIS [28]. Besides giving a physical insight into the device physics, the model provides a guidance for the basic design for the junctionless tri-material gate-stack surrounding-gate MOSFETs.

Fig. 5.1.1: Typical three-dimensional schematic of the junctionless tri-material gate-stack surrounding-gate MOSFETs.

5.2 Model Derivation

3D Schematic of a junctionless tri-material gate-stack surrounding-gate MOSFET is shown in Fig. 5.1.1, which is made of three gate electrodes having different work functions. The reason of replacement of the polysilicon side gates in EJ/straddle-gate structures by metal gates in our structure is the reduction of polysilicon depletion width effects [10] [47].

The gate consists of tri-materials M1, M2 and M3 of lengths, respectively. Since the free carrier concentration is much less than the impurity density for MOSFETs operating in subthreshold regime, the Poisson equation in junctionless tri-material gate-stack surrounding-gate MOSFETs can be divided into three regions and expressed as

2 2

where Nd is the uniform doping concentration of the silicon film. By using the superposition method to solve the above equations, the resultant solution of ψ_i( , )r z (i=1,2,3) can be decomposed into one-dimensional (1D) potential solution Vi(r) and 2D potential solution Ui(r,z), which satisfy the following 2D Laplace equation and 1D Poisson equation. This leads to

( , ) ( ) ( , ) i=1,2,3

5.3 Boundary Conditions

The Poisson equation is solved separately in three regions of the channel by using following boundary conditions:

(A) Electric flux density at the interface of silicon/gate dielectric for three regions is continuous dielectric thickness, toxeff is the effective gate oxide thickness, εsi is permittivity of silicon (εsi = 11.7x8.85x10^-14) and εox is permittivity of oxide (εox = 3.9x8.85x10^-14), (junctionless tri-material gate-stack surrounding-gate) MOSFET, we have three kind materials with work-functions M1, M2 and M3 of the lengths L1, L2 and L3. Therefore,

φsi is the silicon work function, which is given by

φ_si =χ_si+2E^g −φ_B

q (5.3.7)

where Eg is the silicon bandgap at 300 K, χsi is the electron affinity of silicon, φB is the Fermi potential (=V_T×ln N( _d / )n_i ), VT is the thermal voltage (=kT/q), and ni is the intrinsic carrier concentration.

(B) Electric flux density at the center of silicon for three regions is equal to zero

( )

(C) The potential at the source end is

1( , 0) 0 (0 ) 2 tsi

r z r

ψ = = ≤ ≤ (5.3.11)

(D) The potential at the drain end is

3( , ) (0 )

2

g ds si

r z L V r t

ψ = = ≤ ≤ (5.3.12)

(E) Potential and electric field at the interface of the three regions are continuous.

1( , 1) 2( , 1) (0 )

5.4 Potential Model

By using superposition principle with boundary conditions, we obtain the following resultant solution of two-dimensional Laplace equation. By letting

( )

^,

( ) ( )

U r z =R r ×Z z (5.4.2)

Substituting eq.(5.4.2) into eq.(5.2.4), we obtain

+1 0

Thus, the equation (5.4.2) can be rewritten as

( ) ( )

( ) ( )

1

where λn are the eigenvalue, by using boundary condition (A) and equation (5.4.2), it can express as

with Bessel recursion formula, it can be simplified as

0

With cartography method in Fig. 5.4.1, we can obtain the eigenvalue

0x10⁰ 2x10⁶ 4x10⁶ 6x10⁶ 8x10⁶ 1x10⁷

Fig. 5.4.1: The plot of finding eigenvalue with cartography method.

From eq.(5.4.1) and eq.(5.4.8)-eq.(5.4.10), the central potential for junctionless surrounding-gate MOSFET can be expressed as

( )

Material work function will be selected in such a way that work function of the material near the source is highest and that near the drain is lowest for p-channel MOSFET. To verify the device with high-k gate-stack is the same as the device with effective gate oxide, Fig. 5.4.2 shows the potential distribution with both device from the device simulator DESSIS [28]. Fig. 5.4.3 shows the variation of the channel central potential alone channel for different ratios of L1, L2 and L3. A good agreement between the results calculated from our model with those simulated using the device simulator is

obtained. The plot reveals that the minimum surface potential barrier between the source side and the minimum channel position of zmin can be increased for the large ratio of L1 to L2 and L3 such as 2:1:1 shown in Fig. 5.4.3. It is also evident that there are two step-changes of potential along the channel at the interface of M1, M2 and M2, M3. The small difference of voltage due to different gate material keeps uniform electric field along the channel, which in turn improves the carrier transport efficiency that allows us to utilize the benefits of ballistic and overshoot transport in the MOSFETs.

The ratio of three metal gate lengths can be optimized along with the metal work functions and effective oxide thickness for reducing the hot electron effect.

The ratio of three metal gate lengths can be optimized along with the metal work functions and effective oxide thickness for reducing the hot electron effect.

在文檔中 参閘極與環繞閘極金氧半場效電晶體含氧化層介面缺陷電荷與絕緣層堆疊結構之次臨界行為研究 (頁 103-0)