Result and Discussion

Fig. 6.1.2 shows the output characteristics of the tri-material gate-stack MOSFET with different ratios of gate material regions for a gate voltage Vgs set at 1.0 V. Flat characteristics are obtained for the different tri-material gate-stack structures in saturation. Channel doping concentration and the length of the M1 region have a strong influence on the current drive capability of the device. Indeed, it is mainly this region that fixes the output current of the device, as shown in the Ids–Vds curves for the three tri-material gate-stack devices with gate material ratios of 3:2:1, 1:1:1 and 1:2:3. The simulated results for single-material gate-stack MOSFETs are also included for comparison. It reveal that the tri-material device will provide much current drive than single-material device, it also show that the small gate length ratio of L1:L2:L3 will result in large current in comparison to the large ratios like 1:1:1 and 3:2:1.

The output conductances are deduced from these simulations and are shown in Fig.

6.1.3. Output conductance is governed by channel length modulation (CLM) near saturation (low Vds) and by DIBL at high Vds [68] if impact ionization is ignored.

Depending upon the gate material ratios of the tri-material and single-material gate-stack device, Vds values that will govern the CLM and DIBL-dominated regions for tri-material would be different from the ones for single-tri-material. In the CLM-dominated region, single-material device exhibits a lower gd compared to tri-material device since the conduction region under the gate in tri-material device modulates its length [69]. On increasing Vds, once the tri-material device enters the DIBL-dominated region, it exhibits a lower gd tendency compared to the single-material device because of the reduced drain influence on the channel charge [69]. Hence, at high drain bias, tri-material gate-stack MOSFET with the gate tri-material ratio of 3:2:1 and 1:1:1 exhibits

extremely low output conductances when compared for the same physical parameters with corresponding single-material gate-stack MOSFET. However, a minimum conductance is reached at a higher drain voltage, in compliance with their drain current.

Another important parameters studied in this section for analog performance are output resistance (Rout = 1/gd) and early voltage (VEA = Ids×Rout). Fig. 6.1.4 and Fig.

6.1.5 shows the variation of the output resistance and early voltage with the drain bias for the tri-material and single-material gate-stack devices at a gate bias of 1.0 V. Like gd

and Rout, the early voltage VEA is also governed by the CLM effect at low Vds and DIBL effect at high Vds. As shown in the figure that roughly 0.2 < Vds < 0.6 V, which is the CLM-dominated region, it is the single-material gate-stack device that offers a better VEA, but once the drain bias goes above 0.6 V, tri-material device of gate material ratio 1:1:1 shows a marked improvement in the VEA value over single-material device since DIBL is mitigated in tri-material device. A similar explanation holds true for the early voltage curves for tri-material device of gate material ratio 1:2:3 and 3:2:1 with the difference of drain bias range values. Thus, the improvement in VEA at Vds = 2.0 V of tri-material devices [gate material ratio 3:2:1 (VEA = 21.3 V), 1:1:1 (VEA = 23.3 V), 1:2:3 (VEA = 16.8 V)] over single-material devices (VEA = 10.2 V) is attributed to the enhanced vertical gate coupling and the lesser lateral drain influence on drain current.

This reduced effect of the drain bias reduces drain conductance, as shown in Fig. 6.1.3, and thus improves the early voltage. As M1 controls the current drive capability and M3

output conductance, the improvement offered by tri-material device with a gate material ratio 1:1:1 is tremendously enhanced because of a balanced contribution from triple gates (M1, M2 and M3). An improvement by a factor of three is observed in the early voltage of tri-material device with a gate material ratio 1:1:1 as compared to the single-material device with the same physical gate length. The effect of a lower work function

gate toward the drain side in tri-material devices operating in full depletion is like having a low-doped region toward the drain side, which causes an almost negligible variation of channel potential with drain bias in the highly doped region under gate M1. This leads to the reduction of the length of the velocity-saturated region, thereby decreasing the output conductance and increasing the output resistance and early voltage in tri-material gate-stack MOSFETs.

Fig. 6.1.6 shows the impact of the L1 on transconductance of tri- and single-material gate-stack MOSFETs. As L1 increases, transconductance of the device decreases due to the reduction in the ON-state current as discussed previously. It can also be observed that tri-material device possesses higher transconductance as compared with single-material having the same electrical channel length (i.e., total length is the same for both the devices). This is only because of the better suppression in SCEs in case of tri-material transistor. Fig. 6.1.7 shows that, among the three tri-material devices when compared for the same physical gate length but different gate material ratios. One can observe, in subthreshold regime, there is a slight reduction in the value of device efficiency for tri-material device cases. However, a slight reduction of this, which is due to the higher value of Ids, will not affect the performance much in the subthreshold regime. On the contrary, in superthreshold regime, the device efficiency for tri-material device exhibits more capability in translating power into transconductance. Noise margin is also calculated using the voltage transfer characteristics (VTC) of CMOS inverter based on tri- and single-material device as shown in Fig. 6.1.8. The noise margin represents the maximum allowable noise voltage present at the input that will not corrupt the output voltage. Results reveal that CMOS inverter having the gate material ratio 1:1:1 as driver transistor shows superior VTC as compared with the inverter having transistor with gate material ratio 1:2:3 and 3:2:1. In addition, the VTC

for tri-material of gate material ratio 1:1:1 shows narrow transition region as compared with single-material device based inverter circuit. This is only because of the better SCEs as well as the enhanced gate controllability achieved by tri-material of gate material ratio 1:1:1 as compared with other configurations (i.e., gate material ratio 1:2:3 and 3:2:1) and single-material device.

While the aforecited list of important metrics for analog design is very detailed, it can still serve as a useful basis in investigating the significances of further scaling and in discussing several important aspects and subtleties of device modeling.

0 0.4 0.8 1.2 1.6 2

Drain Bias, V

(V) 10

10

10

10

D rain C u rr en t, I

(A)

Single Material L₁:L₂:L₃ = 3:2:1 L₁:L₂:L₃ = 1:1:1 L₁:L₂:L₃ = 1:2:3

t_oxeff = 2 nm t_si = 20 nm L_g = 60 nm V_gs = 1 V y_M1 = 4.8 eV y_M2 = 4.6 eV y_M3 = 4.4 eV

Fig. 6.1.2: Drain current Ids as a function of the drain voltage Vds.

0 0.4 0.8 1.2 1.6 2 Drain Bias, V

(V)

10

10

10

Ou tput Conductance, g

(S )

Single Material

Fig. 6.1.3: Output conductance gd as a function of the drain voltage Vds.

0 0.4 0.8 1.2 1.6 2

Drain Bias, V

(V) 10

10

10

Out p u t Re si st ance , R

( W )

Single Material

Fig. 6.1.4: Output resistance Rout as a function of the drain voltage Vds.

0 0.4 0.8 1.2 1.6 2

Early Voltage, V

(V)

Single Material

T ran con d u ctanc e, g

(mS)

L₁:L₂:L₃=1:2:3

Fig. 6.1.6: Variation of the transconductance with gate bias at Vds = 1.0 V.

10

10

10

10

10

10

10

10

10

10

10

De v ic e E ff ic ie nc y, g

/I

(V

)

Single Material

Fig. 6.1.7: Variation of device efficiency (gm/Ids) with drain current for different gate material ratio.

Out p u t V o ltage, V

(V)

L₁:L₂:L₃=1:2:3

Fig. 6.1.8: Voltage transfer characteristic (VTC) of tri- and single-material gate-stack MOSFET.