Threshold Voltage Model

Historically, the most popular VTH definition used in compact modeling is the gate voltage φB at which the band bending reaches at the silicon conducting path [39], where φB is the difference between the Fermi level and intrinsic level of silicon in the neutral region. Under this condition, the inversion carrier density at the silicon surface equals the density of the doping atoms in the silicon bulk Na. This definition has been physically reasonable and successful in identifying the turn-on condition for bulk devices, where Na -values are in the range of 1x10¹⁶cm^-3.

In order to solve analytical threshold voltage, we need to rewrite coefficients as a linear equation related to VGS. From eq.(3.2.21), eq.(3.2.22) and eq.(3.2.30 ~ 3.2.35), we get

1 2

By using eqns.(3.2.51)-eq.(3.2.56), we can get the minimum potential as a linear equation related to gate bias VGS.

( )

2 achieved. Due to reducing the complicated calculation and its rapid decay of Fourier series coefficients, the first term can dominate the whole series. Thus

2

The largest VTH,i in above equation will dominate the threshold voltage.

3.2.7 Threshold Voltage Model Result

To verify the proposed model, the 3D device simulator “DESSIS” is used to simulate the device. The threshold voltage is extracted for the gate voltage that causes the electron concentration at the position of the minimum central potential to be equal to the bulk doping density. For the fixed positive/negative interface sheet charge density, Fig. 3.2.5 shows how the threshold voltage degradation is affected by the normalized damaged zone for the different diameters of silicon body. The increased damaged zone can further degrade the threshold voltage, because the correspondingly increased interface positive/negative trapped charges will decrease/increase the minimum channel potential barrier [5], which hence results in the roll-off/roll-up of the threshold voltage.

This interface-trapped-charge-induced threshold voltage degradation is called ITTVD.

For the positive interface trapped charges, the small diameter of silicon body of tsi = 10 nm will suffer less ITTVD in comparison to the large diameter of tsi = 30 nm when Ld

increases. This is because the large silicon thickness decreases more minimum central potential barrier than the small silicon thickness for the positive interface charges. On the contrary, for the negative interface trapped charges, the large diameter of silicon body of tsi = 30 nm will undergo less ITTVD when compared to the small diameter of tsi

= 10 nm due to the fact that the small silicon thickness decreases more minimum central potential barrier than the large silicon thickness. The fixed positive/negative interface trapped charge density for the small diameter of silicon body will lessen/enhance ITTVD when the damaged zone increases. Although the small diameter of silicon body is preferred to resist ITTVD caused by the positive charges, the diameter of silicon body should become larger not only to reduce ITTVD by the negative charge but also to enhance the current driving capability by means of the wide cross-sectional area of the channel. Fig. 3.2.6 shows the variation of threshold voltage degradation with the

normalized damaged zone for different oxide thicknesses. The interface positive/negative charges with large damaged zone will bring about great threshold voltage degradation, particularly for the thick oxide thickness. To make the device experience less ITTVD, not only should the thin gate oxide be accounted for but the small damaged zone is desired for the device. Note that when the gate oxide thickness is reduced below 10 nm [40], the gate leakage current caused by the tunneling effects will deteriorate the device performance. The trade-off about keeping the low threshold voltage degradation without increasing the large gate leakage current should be seriously considered in designing the device. Fig. 3.2.7 depicts the dependence of the threshold voltage roll-off on the channel length for both the damaged and fresh devices.

The ITTVD caused by interface trapped charges may be coupled with drain-induced barrier lowering (DIBL). Since the ITTVD caused by the negative trapped charges (i.e., threshold voltage roll-up as shown in Fig. 3.2.6) has an opposing effect to DIBL that causes threshold voltage roll-off for the short-channel device, the threshold roll-off induced by DIBL for the damaged device with the negative trapped charges will be decreased and become less than that for the fresh device as the gate length is reduced.

On the contrary, due to the fact that the ITTVD caused by the positive trapped charges (i.e., threshold voltage roll-off as shown in Fig. 3.2.6) takes the same effect as DIBL, the threshold roll-off induced by DIBL for the damaged device with the positive trapped charges will be enhanced and become more than that for the fresh device. Although the negative interface trapped charge can alleviate DIBL, it will bring about the large operation of threshold voltage and can be an obstacle for low voltage circuit application.

It is worthwhile to point out that, for the small damaged zone of Ld = 10 nm with the longer channel length of Lg > 60 nm (i.e., the smaller normalized damaged zone of Ld/Lg < 1/6), ITTVD can be negligible in comparison with DIBL, and the threshold voltage degradation for all of the three cases will be dominated by DIBL. This clearly

explains why the threshold voltage roll-off for all of the three cases are almost the same as shown in Fig. 3.2.7 as Lg > 60 nm with Ld = 10 nm.

0 0.2 0.4 0.6 0.8 1

Normalized Damaged Zone, L

/L

-0.12

-0.08 -0.04 0 0.04 0.08 0.12

ITTVD ( V )

Solid Line : +Nf Damaged Devise Dash Line : -Nf Damaged Devise Line : Model

Symbol : ISE

-2- : t_si= 10 nm

-,- : t_si= 20 nm -&- : t_si= 30 nm V_ds = 0 V

tox = 2 nm L_g = 60 nm L_s = 0 nm

N_a = 2â10¹⁶ cm^-3 N_d = 1â10²⁰ cm^-3 N^f = 1â10¹² cm-²

Fig. 3.2.5: Threshold voltage degradation versus normalized damaged zone for different diameters of silicon body.

0 0.2 0.4 0.6 0.8 1 Normalized Damaged Zone, L

/L

-0.16

Solid Line : +Nf Damaged Devise Dash Line : -Nf Damaged Devise Line : Model

Fig. 3.2.6: Threshold voltage degradation versus normalized damaged zone for different oxide thicknesses.

Threshold Voltage R oll-o ff (V )

Line : Model Symbol : ISE

N_d = 1x10²⁰cm^-3 N_a = 2x10¹⁶cm^-3 N_f = 1x10¹²cm^-2

-&-

:

-,-

:

Fig. 3.2.7: Threshold voltage roll-off versus gate length for both fresh and damaged devices.