System Architecture of SIMO DC-DC Converter

According to the proposed controlling sequence-II and the LDPCC technique, the architecture of the proposed SIMO converter is illustrated in Fig. 33. As previous analysis of switch number, the minimum number of switch is shown in the top of Fig. 33. The main switch SW_N and freewheeling switch SW_F construct paths 3 and 6 of controlling sequence-II.

Switches SW_K1~SW_Kn and SW_T1~SW_Tm are used to extend and isolate output terminals V_OK1~V_OKn and V_OT1~V_OTm. Therefore, the total number of power switch is equal to the number of output terminals pluses two. Output voltages are detected by error amplifier array via output divider array. The output signals V_EK1~V_EKn and V_ET1~V_ETm of error amplifier array connect to the input terminals of LDPCC circuit for generating load dependant peak current signal V_Ipeak. Moreover, the LDPCC circuit also generates current signals I_EK1~I_EKn and I_ET1~I_ETm which are used to be discharging current sources in charge reservation circuit. Since the charge reservation circuit uses the output current I_SEN of current sensor and the LDPCC current signals I_EK1~I_EKn and I_ET1~I_ETm as charging and discharging current sources respectively, the storage charge on indicative capacitors C_IK1~C_IKn and C_IT1~C_ITm of charge reservation circuit can fully depend on inductor current (I_L) and load variations. Therefore, the voltages V_IK1~V_IKn and V_IT1~V_ITm on indicative capacitors C_IK1~C_IKn and C_IT1~C_ITm are used to

V_SWN

Fig. 33. The proposed load-dependent peak current control SIMO DC-DC converter with hysteresis mode for high power conversion efficiency and minimum cross regulation.

compare with output signals V_EK1~V_EKn and V_ET1~V_ETm of error amplifier array for deciding the energy delivering duration of each output terminal. The time interval of path 3 is decided

by the comparison of current signal V_RS and LDPCC signal V_Ipeak. The output signals CM_R, CM_K1~CM_Kn, and CM_T1~CM_Tm of comparator array are used to enable control sequence-II in control logic circuit and generate the MOSFET’s driving signals V_SWF, V_SWN, V_SWK1~V_SWKn, and V_SWT1~V_SWTm via dead-time controller and driver. For current accumulation issue, power comparator and delta-voltage generator continuously monitor the voltage deviation of output terminals and generate output signals mode₁~mode_n to control mode switch of control logic.

Chapter 3

Design and Analysis of Proposed SIMO DC-DC Converter

3.1 LDPCC Decision Circuit

V

_EKi

Outputs of EA

array in buck 1: N: M V-I converter

R

_Ki

V V

_EK2EK1

I

_EKi

I

_EK2

I

_EK1

V

_ETj

1: N: M V-I converter

R

_Tj

V V

_ET2ET1

I

_ETj

I

_ET2

I

_ET1

R

_peak

I

_peak

I

_DC(min)

V

_Ipeak

EA

EA

Outputs of EA array in boost

Fig. 34. The implementation of the proposed LDPCC circuit which dynamically adjusts the peak current level according to the value of load current.

As previous discussion in [2], the peak inductor current level (I_DC) is used to provide pre-charged energy in inductor L for large load variations. A high value of peak current has sufficient capability for driving large load condition. However, the disadvantage of high peak current level (I_DC) is inefficient power conversion efficiency at light load condition.

Oppositely, a lower value of peak current has good power conversion efficiency at light load

condition while converter needn’t high capability to handle large load current step. Therefore, the peak current level must adjust with variation of load current. Besides, peak current level also affects cross-regulation in SIMO converter owing to the over-storage charge in inductor L. To improve the power conversion efficiency at light loads and to reduce the effect of cross-regulation, a peak current decision circuit is depicted in Fig. 34. Where the suffix i is from 1 to n for buck output terminals and the suffix j is from 1 to m for boost output terminals.

The peak current decision circuit dynamically adjusts peak current level V_Ipeak according to variation of output load conditions. All output voltages of feedback error amplifiers are converted current signals by the voltage to current (V-I) converters. Each V-I converter generates two current signals with a conversion ratio (1: N: M). The current signals I_EK1~I_EKn and I_ET1~I_ETm (where the suffix index i is 1 to n for buck output terminals and the suffix index j is 1 to m for boost output terminals) are used to work as discharging currents of the charge reservation circuit. The other current signals are summed to generate the LDPCC current (I_peak), which varies with load currents. Furthermore, to avoid the zero inductor peak current, a minimum peak inductor current is set by a current source I_DC(min). The non-inverting input of the comparator is decided by the voltage signal V_Ipeak, which is generated by flowing two current signals (I_peak) and I_DC(min) through the resistor R_peak. The value of LDPCC level V_Ipeak is determined by (19).



Peak DC(min)



peak

Ipeak R I I

V   (19)

The input voltages of the V-I converters are V_EK1~V_EKn and V_ET1~V_ETm from the error amplifier array that indicates the load conditions of all multiple buck and boost output terminals. The value of peak current decision circuit varies with the variation of load current. At very light load, the value is kept at value of I_DC(min) and thus current level (I_peak) of freewheeling stage can be reduced compared to that with the fixed inductor current level (I_DC) in conventional design [2]. That is, the light-load efficiency can be improved without over-storage charge in

Fig. 35. The transient simulation result of proposed LDPCC circuit which uses dual-error output signals as an example.

the inductor L. For a dip in one of the output terminals due to an increase in load current, for example, the control system increases the duty ratio, which in turn indirectly causes an increased peak inductor current level V_Ipeak. The energy stored in the inductor L is gradually increased to minimize cross-regulation due to the LDPCC level at heavy load conditions.

Similarly, the period of freewheeling stage occupies little duration of every switching cycle.

The order of the system is still kept as one, and the power dissipation is always kept small.

Therefore, the P-I compensator can ensure the stability of the system, and the heavy-load power conversion efficiency can be kept high. The transient simulation result of LDPCC circuit, which uses dual-error output signals as an example, is shown in Fig. 35. While the output load condition (I_OT) suddenly changes to heavy load condition, the output signal (V_ET) of error amplifier increases to a rated value for generating LDPCC level V_Ipeak. When the output load condition (I_OK) is increase at the same time, the output signal (V_EK) of error amplifier also increases the LDPCC level V_Ipeak. Therefore, the LDPCC level V_peak depends on

output load conditions and the energy stored in the inductor L is gradually increased to minimize cross-regulation and handle higher power capability due to the LDPCC level at heavy load conditions.

3.2 Current Sensor and Charge Reservation Circuits

Fig. 36. The current sensor of [2 and 3] is composed by a fully symmetrical matching structure.

The current sensor shown in Fig. 36 [2 and 3] has a proportional register RS which is N times of the sensing resistor RSEN. The current sensor is composed by a fully symmetrical matching structure. Sufficient accuracy and high bandwidth is used to follow output current variations. To achieve the LDPCC technique, the current sensor cannot be turned off during the whole switching cycle. Thus, the freewheeling power MOSFET as illustrated in Fig. 36 is connected between the input power source VIN and the node VX at the expense of power

conversion efficiency during the freewheeling stage. The current sensor is realized by the matched PMOS transistors M_A2 and M_B2 which are used to enforce the same voltage at node V_x and node V_y. The PMOS transistors M_A2 and M_B2 are biased in the saturation region. Two small and equal biasing current force the PMOS transistors M_A2 and M_B2 to have the same threshold voltage. Self-bias loop is composed by transistors M_A4, M_A3, M_A1, and M_B1. Sensing current is generated via transistor M_B4. The simulation result of current sensor is shown in Fig.

37 and a test pattern of inductor current (I_L) is given by piecewise-linear (PWL) waveform in HSPICE simulation tool. The sensing signal converts the current scale (I_sense) into voltage scale (V_RS) for detecting LDPCC level V_Ipeak. The mirrored current signal (I_sense) is used to charge the indicative capacitors C_IK1~C_IKn and C_IT1~C_ITm of charge reservation circuit which is shown in Fig. 38.

Fig. 37. The simulation result of current sensor.

V

_IN

Fig. 38. The proposed charge reservation circuits and charge monitor circuit for reducing output ripple.

The architecture of the charge reservation circuit is shown in Fig. 38. The sensing current (I_sense) is converted to the voltage V_RS, which is used to compare with the LDPCC level V_Ipeak as illustrated in Fig. 33. The sensing current (I_sense) is also used to determine the individual

duty cycle of each buck or boost output terminal. Thus, there are n and m charge monitoring circuits in the charge reservation circuit. The indicative capacitors C_IK1~C_IKn and C_IT1~C_ITm are used to monitor the buck and boost output voltages, respectively. The charge monitor circuit in the sub-block is also shown in Fig. 38. When the voltage of driving signal V_SW is set to low, sensing current (I_sense) flows into indicative capacitor C_I to indicate the energy delivering condition of one of buck or boost output voltage. Once the voltage of driving signal V_SW is changed from low to high state, the discharging current (I_in), which comes from the LDPCC circuit, starts to discharge indicative capacitor C_I. Thus, the voltage ripples ΔV_IK1~ΔV_IKn and ΔV_IT1~ΔV_ITm on indicative capacitors C_IK1~C_IKn and C_IT1~C_ITm can monitor the status of the buck and boost output voltages. As a result, the duty cycle can be determined by the voltage V_I on indicative capacitor C_I and the output voltage V_EKi (or V_ETj) of error amplifier array after the operation of comparator array in Fig. 33.

Assume that the value of voltage ripples ΔV_IKi and ΔV_ITj is k_Ki and k_Tj times that of output ripples ΔV_OKi and ΔV_OTj for the buck output terminal i and boost output terminal j, where the suffix i is 1 to n for buck output terminals and the suffix j is 1 to m for boost output terminals.

The buck and boost output ripples ΔV_OKi and ΔV_OTj express as (20) by voltage ripples ΔV_IKi and ΔV_ITj on the indicative capacitors C_IKi and C_ITj in charge reservation circuit.

IKi

The value of voltage ripples ΔV_IKi and ΔV_ITj are set within the input common-mode range of the comparator array in Fig. 33. Besides, the value of inductor current (I_L) is N times that of sensing current (I_sense), which is the sensing current for buck and boost output terminals. Thus, the values of indicative capacitors C_IKi and C_ITj in the charge reservation circuit are given by (21) and (22), respectively.

OTj R_T1~R_Tm in the V-I converters must depend on output load condition. As a result, the charge reservation circuit in the SIMO DC-DC converter can accurately discharge storage charge in indicative capacitors C_IK1~C_IKn and C_IT1~C_ITm. The discharging current sources I_EKi and I_ETj operational trans-conductance amplifier (OTA) can be express as (24) by adopting equation (21).

where G and β_Ki are the trans-conductance of error amplifier and the ratio of voltage divider, respectively. Then, as shown in (25), the discharging current source I_EKi is equal to that the error signal V_EKi is divided by internal resistor R_Ki.

 

Differentiating both sides of (25) by the inductor current (I_L) and setting the value equal to one, (26) is derived to get a discharging current source I_EKi that is proportional to output load current. Consequently, (27) defines the value of resistor R_Ki in charge reservation circuit

for buck output terminals.

Similarly, the value of resistor R_Tj for boost output terminals can be expressed as (28).

ITj ensure that discharging current sources I_EKi and I_ETj in LDPCC circuit are proportional to load current condition of buck and boost output terminals. The discharging current sources I_EKi and I_ETj are expressed as equation (29) and (30) for buck and boost output terminals, respectively.

Ki reservation circuit can accurately decide the duty cycle of the buck or boost output terminals.

The simulation result of charge reservation circuit is shown in Fig. 39. The output signals V_EKi and V_ETj of error amplifier array indicate the output voltage deviation. Since the indicative capacitors C_IKi and C_ITi are charged and discharged by sensing current I_sense and LDPCC circuit sources I_EKi and I_ETj, the voltages V_IKi and V_ITj on indicative capacitors act sensing ripple of output terminals and compare with the output signals V_EKi and V_EKj of error amplifier array for detecting operation duty cycle of each output terminal.

Fig. 39. The simulation result of the proposed charge reservation circuit.

3.3 Logic Control Circuit with Automatic Mode Switch for Avoiding Instability Problem

The control logic generator with automatic mode-switch controller is depicted in Fig. 40.

It generates logic control signals D_SWN, D_SWF, D_SWK1~D_SWKn, and D_SWT1~D_SWTm for driving power switches according to system clock V_CLK and output signals CM_Ki, CM_R, and CM_Tj of comparator array. The operation of the control logic is divided into four durations of current paths 1, 3, 4, and 6, which sustain for the four charge-delivering paths in Fig. 25. At the beginning of path 1, the system clock V_CLK of control logic generator is triggered by a positive edge and 90% duty cycle of system clock V_CLK. The state of logic control signal D_SWKi is set to low state and converted to driving signal V_SWKi for delivering charge from supply source V_IN

D Q

Fig. 40. The control logic generator with the mode switch controller.

to buck output terminal VOKi. The input signal CMKi of control logic circuit, where the suffix i is from 1 to n for buck output terminals, is from output signals of related comparator i in Fig.

33, which decides the duty cycle of buck output terminal i. At the same time, the inductor current (I_L) is increased with a positive current slope ((V_IN-V_OKi)/L). According to charge reservation circuit operation, current sensor senses inductor current (I_L) for charging indicative capacitors C_IKi and C_ITj of charge-reservation circuit. Therefore, the indicative capacitor C_IKi is charged by sensing current I_sense of current sensor. When the charging voltage V_IKi on indicative capacitor C_IKi is larger than output signal V_EKi of error amplifier array in Fig.

33, the output signal CM_Ki of comparator array changes to a low state and path 1 then turns off. Since the control logic unit combines the system clock V_CLK and comparator output CM_Ki

as trigger signal CK_OUT, Path 3 starts to ensure sufficient energy to be stored in the inductor L at the negative edge of comparator output CM_Ki. That is, the inductor current (I_L) is increased to the LDPCC level (I_peak).

In path 3, the LDPCC signal V_Ipeak in (19) which defines charge requirement according to the LDPCC circuit in Fig. 34 and the value of current signal V_RS in Fig. 36 are used to determine the time interval of output signal D_SWN for increasing the inductor current (I_L) to the LDPCC level (I_peak) until the value of current signal V_RS is large than that of LDPCC signal V_Ipeak. That is, the output signal D_SWN is set to high state for increasing the value of inductor current (I_L) to LDPCC level (I_peak) until the value of current signal V_RS is large than that of LDPCC signal V_Ipeak. However, the time interval of output signal D_SWN may be zero if the inductor current (I_L) is increased to exceed the LDPCC level (I_peak) during path 1. This condition is caused by the heavy load condition at buck output terminals and light load condition at boost output terminals. This means that the inductor current level (I_L) is high enough to provide sufficient energy to the multiple boost output terminals after path 1. There is no need to store more charge in the inductor L since it may cause current accumulation issue in Fig. 41. Therefore, a hysteresis mode which is shown in Fig. 26 is proposed to address the current accumulation issue and provide a new charge-delivering path rather than path 1.

Once the value of current signal V_RS is large than that of LDPCC signal V_Ipeak, comparator output CM_R changes to low state and path 3 turns off. Path 4 then is enabled by negative edge of comparator output CM_R and starts to deliver charge to boost output terminals.

At the same time, the inductor current (I_L) is decreased with a negative current slope ((V_OB-V_IN)/L) which according to the load condition of the boost output terminals. Similarly, according to charge reservation circuit operation, indicative capacitor C_ITj is charged by sensing current (I_sense) of current sensor. When the charging voltage V_ITj on indicative capacitor C_ITj is larger than output signal V_ETj of error amplifier array in Fig. 33, the output

(1)

(4) (3)

(6)

PWM mode

I_peak IL (A) VSWTj

VSWN

VSWKi

V_SWF

Buck Boost FW

TS

0 time

(1) (6)

(4)

2TS 3TS

Current accumulation

Hysteresis mode

Buck Boost FW

Fig. 41. The timing diagram of the transition from the PWM mode to the hysteresis mode.

signal CMTj of comparator array changes to low state. Once comparator output CMTj is changed to a low state when the value of charging voltage V_ITi is larger than output signal V_ETj of error amplifier array, the charge-delivery to the boost output terminals is completed. Then the controlling sequence-II enters path 6 named as freewheeling stage. That is, the surplus energy is reserved in the inductor L. The longer the period of the freewheeling stage is, the lower the power conversion efficiency. Owing to the adjustment of the LDPCC circuit, the inductor current level (I_L) at the freewheeling stage is kept at a low level which is limited by a minimum current level I_DC(min) and thus the conduction loss can be reduced at light load conditions. All the output signals D_SWK1~D_SWKn, D_SWN, D_SWT1~D_SWTm, and D_SWF of the control logic circuit are converted by the dead-time controller and driver circuit which is shown in Fig.

33 to the gate driving signals V_SWN, V_SWF, V_SWK1~V_SWKn, and V_SWT1~V_SWTm which are used to control the power MOSFET switches SW_N, SW_F, SW_K1~SW_Kn, and SW_T1~SW_Tm.

However, the mentioned current accumulation issue which is illustrated in Fig. 41 still exists in the structure of SIMO converter. When the output power of buck output terminals is

larger than that of boost output terminals, the current accumulation occurs. The charge from supply source not only delivers to the buck terminals but also store charge in the inductor L during path 1 operation. The only way to release storage charge in inductor L is to transfer storage charge to boost terminals during path 4 operation. Thus, when charge deliver to boost terminals are smaller than that of buck terminals, the inductor current level (I_L) is going to increase higher than the LDPCC level (I_peak). Owing to the current accumulation in inductor L, the sensing current (I_sense) also increase to high value. Therefore, the charging voltage V_ITj on the indicative capacitor C_ITj of charge reservation circuit rapidly increases during short period.

The operating duration of boost terminals becomes much smaller than the original due to the highly inductor current level (I_L). This situation causes that the comparator array is not able to react to such a small operating duration. Thus, the accumulated current causes serious cross-regulation and poor conversion efficiency at light load conditions.

To address this problem, it is important to provide other releasing path to alleviate the instability. Hence, a new current path which is path 0 and named as hysteresis mode is proposed in Fig. 26. During operation of hysteresis mode, original path 1 in PWM mode is changed to path 0 to force the delivering current to flow through freewheeling switch SW₆ to the buck terminals. Therefore, the delivering energy of the buck terminals does not cause current accumulation in the inductor L. Thus, the buck terminals works as a hysteresis buck

To address this problem, it is important to provide other releasing path to alleviate the instability. Hence, a new current path which is path 0 and named as hysteresis mode is proposed in Fig. 26. During operation of hysteresis mode, original path 1 in PWM mode is changed to path 0 to force the delivering current to flow through freewheeling switch SW₆ to the buck terminals. Therefore, the delivering energy of the buck terminals does not cause current accumulation in the inductor L. Thus, the buck terminals works as a hysteresis buck

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