Maximum Voltage Selector Circuit and Adaptive Body Switch (ABS) Circuit

To fully turn on and off power switches of output terminals, the supply voltage of dead-time controller and driver circuit must connect to the highest voltage level (V_MAX) of boost terminals. Therefore, a voltage comparator array usually designs into the maximum voltage selector circuit for detecting the highest output voltage (V_MAX). Large number of boost terminals increases higher operation current and complex circuit design for biasing voltage comparator. In order to reduce the power consumption of maximum voltage selector circuit and simplify composed structure of voltage comparator, a new and simplest multiple-input voltage comparator as shown in Fig. 51 is proposed to detect the highest voltage level (V_MAX)

on all of boost terminals.

As illustrated in Fig. 51, transistors M_B1~M_B3 and bias current (I_B) compose the biasing loop, the controlling logic circuits are biased by the maximum voltage (V_MAX). The biasing voltage (V_BP) is used to clamp the gate biasing voltage of each input terminal for comparing the detecting voltage (V_M) and input terminals V_IN and V_OT1~V_OTj. At the initial condition of

Fig. 51. The proposed maximum voltage selector circuit for dead-time and driver circuit.

V_IN V_OT1

V_MAX V_OT2 V_OTj

D_n D₁ D₂ D_j

Fig. 52.The non-overlapping power switches.

power on procedure, the detecting voltage (VM), input terminals VOT1~VOTj, and maximum voltage (V_max) are zero. The input terminal V_IN, which comes from battery or supply source, is only the highest voltage (V_MAX) in maximum voltage selector. The voltage difference between detecting voltage (V_M) and input terminal V_IN cause the gate-source voltage V_GS of transistor M₃ is higher than that of transistor M_B1. Therefore, the drain current (I₁) of input terminal V_IN is larger than biasing current (I_B). That is, the current (I_n) is larger than detecting current (I_sum) and the detecting signal (V_n) of detecting logic is then set to low state. Transistors S₁, S₂, and M₄ turn on, the detecting voltage (V_M) is charged closed to the input terminal V_IN via transistor M₄. The maximum voltage (V_MAX), which provides the supply voltage of driver, is connected to the input terminal V_IN by a non-overlapping power switches which is illustrated in Fig. 52.

In the meanwhile, in order to get the information of input terminal V_IN, the detecting current (I₁) is added to detecting current (I_sum) through S₁ and the detecting current (I_n) equals to 2I₁ for stabilizing the logic state during the input terminal V_IN is the highest voltage. Moreover, owing to other input terminals are smaller than detecting voltage (V_M), the input MOSFETs which connect to input terminals, such as transistors M_T1~M_T3, are biased at cut-off region.

Thus, the detecting current (I_Tj) is zero and smaller than detecting current (I_sum), the logic state of detecting signals V_j is then set to high state for disabling the connection from other input terminal V_OTj and saving power consumption.

Owing to the detecting current (I₁) of the input terminal V_IN is added to detecting current (I_sum), the voltage difference between detecting voltage (V_M) and the next input terminal V_OTj must be higher enough to generate that detecting current (I_Tj) is larger than detecting current (I_sum). Therefore, when the input terminal V_OTj ramps up to the defined voltage level and is higher than detecting voltage (V_M), the detecting current (I_T) is larger than detecting current (I_sum) for generating low state of detecting signal (V_j). Since detecting signal (V_j) changes to low state, transistors S_T1, S_T2, and M_T4 turn on, the detecting current (I_Tj) is added to detecting current (I_sum) and detecting current (I_T) equals to 2I_Tj for stabilizing low state of detecting

signal (V_j). At the same time, the detecting current (I_n) which is generated from input terminal V_IN is smaller than detecting current (I_sum) and detecting signal (V_n) sets to high state. The detecting current (I₁) then removes from detecting current (I_sum), the maximum voltage (V_MAX) disconnect to input terminal V_IN and then connects to input terminal V_OTj. In the meanwhile, the detecting voltage (V_M) is charged closed to input terminal V_OTj by transistor M_T4. Owing to the highest voltage changes to input terminal V_OTj, the input MOSFETs which connects to other input terminals, are biased at cut-off region. The maximum voltage selector circuit causes that only the biasing loop and the highest input terminal has biasing current. Therefore, the minimized biasing current and minimum power consumption can be achieved. The simulation result of the maximum voltage and total biasing current is shown in Fig. 53.

Fig. 53. The simulation result of maximum voltage selector circuit.

In CMOS fabrication technologies, single-well process is popularly used. Fig. 54 shows the cross section of single n-well CMOS process. Node B_P is the n-well biasing terminal for p-MOSFET transistor substrate and node B_N is the p-substrate biasing voltage for n-MOSFET

Fig. 54. The cross section of n-well CMOS process.

Fig. 55. The latch-up and equivalent latch-up circuit in n-well CMOS process.

transistor. To prevent the conduction of the parasitic PN junction diodes (such as D₁ and D₂) and avoid latch-up, node B_P should be connected to the highest voltage (V_MAX) of SIMO converter, which is the supply voltage in most cases. Similarly, node B_N should be connected to the lowest voltage of SIMO converter, which is usually the ground [43]. When the substrate voltage is improperly handled, leakage current becomes a serious problem. This is especially critical for the systems adopting variable bias at drain and source terminals.

Because the voltage of drain terminal D_P of p-MOSFET transistor can be possibly higher or lower than that of source terminal S_P, the leakage problem can be hardly prevented if the substrate is tied to a fixed voltage node. More seriously, parasitic bipolar transistor in a

CMOS process form a latch-up circuit, illustrated in Fig. 55. When the voltage of node V_X is lower than that of output terminal V_OT, the substrate voltage in the n-well should be tied to output terminal V_OT to avoid leakage. However, if voltage of node V_X becomes higher than that of output terminal V_OT, the emitter voltage of parasitic PNP transistor will be higher than that of node B_P, and a positive current feedback loop will be activated. The risk of having devastating latch-up increases substantially.

Fig. 56. The proposed ABS circuit for p-MOSFET’ body bias.

Owing to the dead-time insert into the controlling sequence of SIMO converter, the voltage spike occurs on the node V_X which is shown in the right-side of Fig. 48. During the time interval of dead-time process, all of power switches turn off. Since the inductor L tries to keep current running the same direction and magnitude than before, the inductor current (I_L) turns to charge the parasitic capacitor C_par on node V_X. Therefore, a large volume of voltage spike appears and higher than that of output terminals. A back-to-back isolated rectifier in output multiplexers are used in [1], but sacrifice the power conversion efficiency for avoiding the lower positive output voltage would always clamp the higher one. Therefore, in order to address leakage current and potential latch-up of p-MOSFET, the adaptive body switch (ABS) circuit as illustrated in Fig. 56 is necessary and important to connect the body terminal of p-MOSFET to the highest voltage level.

Fig. 57. The simulation result of proposed ABS circuit.

However, the different requirement with maximum voltage selector of driver, a rapidly response and ultra-low power consumption are major demand of ABS circuit. A simplest and low power consumption voltage detector is presented for rapidly selecting the maximum voltage level of body terminal during the switching duration of dead-time. Transistors MB1~MB3 compose the biasing circuit. A symmetric common-gate input stage which separately composed by transistor input pairs M1, M3, and M2, M4 form the input voltage detector. For the operation of ABS circuit, transistor M1 forms the diode connection and biased by transistor MB1. A dropping voltage generates gate-source voltage VGS of transistor M1 and be used to bias transistor M3. Once the gate-source voltage VGS of transistor M3 is slightly higher or lower than that of transistors M1, the transistor M3 can be turned on or off through the designed transconductance gm3 of transistor M3. Thus, full symmetric structure which is used to detect the drain and source terminals of p-MOFET is composed of transistors M1~M4. The biasing current clamps power consumption owing to limited value of biasing current (IB). Transistors M1 and M3 form the input pair to detect the condition that voltage of output terminal VOT is larger than that of node VX and connect the output terminal VOT through transistor M3. Transistors M2 and M4 detect the condition that node VX is larger than output

terminal V_OT and connect the node V_X through transistor M₄. Therefore, when the voltage level of node V_X is larger than that of output terminal V_OT during the time interval of dead-time process, transistor M₄ is turned on and the body terminal V_B connects to node V_X. Contrarily, when the voltage level of node V_X is smaller than that of output terminal V_OT during paths 4 or 3, the body terminal V_B connects to output terminal V_OT. The simulation result is shown in Fig.

57. A triangular waveform and a DC level are used to test the performance of proposed ABS circuit. The result shows only 20mV deviation from the highest voltage level and the accurately compares the voltage level of terminals V_X and V_OT.