Delta-Voltage Generator

Moreover, the inverse signal S_X of output signal mode_X inhibits the related current signals I_AKX and I_BKX. As a result, summation current I_MK2 can be expressed as (40)

) I_BKX(n) are the current signals by the n^th operation of the second loop according to the priority of load condition. Once current I_MK2(n) is smaller than current I_MT2, output signal EN₂ of comparator CP₂ is set back to low state. That is, the charge-detection process is ended, and the proposed converter can really avoid the current accumulation and minimize the output ripples of the buck output terminals in hysteresis mode. The hysteresis mode operates until current depend on the definitions of equations (34) and (35) to generate the different inductor current slopes for the smooth switching between hysteresis and PWM operation modes. In order to meet the input common-mode range of delta-voltage generator and measure buck and boost output voltages, two delta-voltage amplifiers with different input types are proposed for the

Fig. 63. The proposed novel delta-voltage generator is used to generate the intermediate value according to the multiple buck output load conditions.

Fig. 64. The proposed novel delta-voltage generator is used to generate the intermediate value according to the multiple boost output load conditions.

amplifier with multiple-output voltages including V_OK1~V_OKn and supply voltage V_IN is depicted in Fig. 63. The block of the V_GS cancellation is used to remove the V_GS term in the difference voltage between V_IN and V_OKi. The delta-voltage amplifier with multiple output voltages is used to generate the intermediate values. The intermediate values V_INK and V_K1~V_Kn in delta-voltage amplifier of buck output terminals are expressed as (41). Similarly, for the multiple boost output terminals, the amplifier with multiple output voltages as shown

Fig. 65. The differential transconductance amplifier for the generation of the inductor current slope.

in Fig. 64 can generate intermediate values. The intermediate values V_INT and V_T1~V_Tm in delta-voltage amplifier of boost output terminals are expressed as (42). Thus, the current slopes m_Ki and m_Tj can be derived as (41) and (42) which are implemented by the differential transconductance amplifier as illustrated in Fig. 65. The input signals V_inp and V_inn of differential transconductance amplifier are connected to the output terminal of the delta-voltage generator. Therefore, the current slope m_K1~m_Kn and m_T1~m_Tm of buck and boost output terminals are derived as (43) and (44), respectively.

 

 terminals of the power comparator circuit in Fig. 61. Therefore, the smooth transition between the PWM and hysteresis modes can be determined.

Chapter 5

Measurement Results

The proposed SIMO DC-DC converter with the LDPCC technique was implemented in TSMC 0.25μm 2P5M technology. The micrograph of the SIMO DC-DC converter with 4 output terminals is shown in Fig. 66. The supply voltage is 1.8V. The pre-defined output voltages are 1.25V and 1.35V for the two buck output terminals and 2.0V and 2.25V for the two boost output terminals, respectively. The measured inductor current waveform (I_L) of the PWM mode at heavy loads is shown in Fig. 67. The ac coupling measurement of LDPCC level V_Ipeak clearly shows the controlling sequence-II in the inductor current (I_L), which is similar to the description in the previous section as illustrated in Fig. 25.

SW

_N

SW

_T1

SW

_T2

SW

_F

SW

_K1

SW

_K2

Driver &

dead time controller

Control logic

Error amp.

array Comparator

array BG &

Current source Load dependant

Delta-voltage generator Charge reservation

Power comparator

R

_SEN

1 8 0 0 µ m

2100 µm

Fig. 66. Micrograph of the proposed SIMO converter and the chip size is 1800*2100μm².

VOT1=2.23V VOK1=1.23V VOT2=1.98V

V_Ipeak=125mV The proposed sequence II in PWM mode

mK1

mK2

mN

mT1

mT2

mF

Fig. 67. The inductor current controlling sequence measured waveform with heavy loads.

Fig. 68. The measurement of load regulation and cross-regulation when a stepping load (10mA to 100mA) at the buck output terminal VOK1.

Fig. 69. The measurement of load regulation and cross-regulation when a stepping load (10mA to 100mA) at the buck output terminal VOK2.

Fig. 70. The measurement of load regulation and cross-regulation when a stepping load (10mA to 100mA) at the boost output terminal VOT1.

Fig. 71. The measurement of load regulation and cross-regulation when a stepping load (10mA to 100mA) at the boost output terminal VOT2.

The measurements of load transient and cross-regulation are shown in Fig. 68~71. As the measurement results which are shown in Fig. 68 and 69, a stepping load condition (10mA to 100mA) is added to buck output terminals V_OK1 and V_OK2, respectively. Since the output power of buck output terminals is larger than that of boost output terminals, the hysteresis mode is enabled for avoiding the current accumulation issue. Hence, the output terminals V_OK1 and V_OK2 are directly regulated by path 0 which turns on the freewheeling switch M_SWF and isolation switches M_SWK1 and M_SWK2 at the same time. However, the output ripples of terminals V_OK1 and V_OK2 are increased by path 0 since the inductor L has been passed.

Therefore, large output capacitors C_OK1 and C_OK2 are necessary to reduce output ripples, but greatly decrease the transient response at stepping load transition. Besides, the noise which comes from large ripple of buck output terminals V_OK1 and V_OK2 couples to other output terminals and lowers lower load-regulation and cross-regulation. Similarly, a stepping load condition (10mA to 100mA) is respectively added to boost output terminals V_OT1 and V_OT2 which are shown in Fig. 70 and 71. Since the output power of buck terminals is smaller than that of boost terminals, the hysteresis mode is disabled and PWM mode is used to regulate output voltages. Output ripple of PWM mode is smaller than that of hysteresis mode.

Since large information was measured, the statistic charts are used to describe the performance of the proposed converter. The cross-regulation charts of the buck and boost output voltages are shown in Fig. 72 and 73, respectively. In Fig. 72, the load current of 50mA is added to the boost output terminals in order to show the cross-regulation of different operation modes. This indicates that the hysteresis mode increases the cross-regulation from 0.07% to 0.22%. Similarly, the cross-regulation of the boost output V_OT1 is shown in Fig. 73.

It is slightly increased from 0.05% to 0.35% in the hysteresis mode. It is smaller than the value of 0.79% in the pervious works. The line- and load-regulation charts of the buck output in PWM and hysteresis modes are shown in Fig. 74 and 75. In the PWM mode, the boost converter is operated at heavy loads. Contrarily, in the hysteresis mode, the boost converter is operated at light loads. The line-regulations of the buck output voltages are smaller than 0.8%/V, and the load-regulations of the buck output voltages are smaller than 2% in the two operating modes. Figure 76 and 77 show the boost output voltages in the PWM and hysteresis modes. The results depict that the line- and load-regulations between the two modes are similar. The load-regulations of the boost output voltages are smaller than 1%, and the line-regulations of the boost output voltages are smaller than 0.5%/V. The output ripples of the buck and boost output voltages are depicted in Fig. 78 and 79. In the PWM mode, the output ripple is controlled by the values of the inductor and output capacitor, and thus the

value is smaller than 4mV_P-P. In the hysteresis mode, the output ripple of the buck output voltages is increased to 22mV_P-P, and the output ripple of the boost output voltages is increased to 6mV_P-P. The power conversion efficiency is shown in Fig. 80. The PWM operation with load-dependent peak-current control has improved highly power conversion efficiency from 85% to 93%. In the hysteresis mode, due to the energy delivering path without flowing through the inductor, the conversion efficiency drops to 80%~85%. The performance of the SIMO DC-DC converter is summarized in Table II.

0.0 0.1 0.2 0.3 0.4

20 40

60 80

100

10 20 30 40 50 60 70 80

Cross regulation at Buck output (%)

VOK2 output current (mA) VOK1 o

utput c urrent (

mA)

Cross regulation at VOK2

Fig. 72. The cross-regulation at the buck output V_OK2 in the PWM and hysteresis modes.

Hysteresis mode

PWM mode

0.0

Cross regulation at boost output (%)

VOT1 output current (mA)

Fig. 73. The cross-regulation at the boost output V_OT1 in the PWM and hysteresis modes.

1.19 Line- and Load-regulation at VOK1 in PWM mode

Fig. 74. The buck outputs operate in the PWM mode when boost outputs operate at heavy loads.

Hysteresis mode

PWM mode

1.20

Line- and Load-regulation at VOK1 in Hys-mode

Fig. 75. The buck outputs operate in the hysteresis mode when the boost outputs operate at light loads.

Fig. 76. The boost outputs in the PWM mode when the buck outputs operate at light loads.

2.20 Line- and load-regulation at VOT2 in hysteresis mode

Fig. 77. The boost outputs in the hysteresis mode when the buck outputs operate at heavy loads.

Fig. 78. The output ripples estimation of buck output in the SIMO converter.

Hysteresis mode

PWM mode

0

Fig. 79. The output ripples estimation of boost output in the SIMO converter.

78

The efficiency chart of SIMO DC-DC converter

Fig. 80. The power conversion efficiency of the SIMO DC-DC converter with the LDPCC technique.

Hysteresis mode

PWM mode

Hysteresis mode

PWM mode

Table. II. Summary of the performance.

Supply voltage 1.8V @ temperature = 0 ^oC ~ 80 ^oC

Inductor 10 μH (±10%)

Filter capacitor 33 μF with low ESR (small than 50mΩ)

Switching frequency 660 kHz

Process TSMC 0.25μm 2P5M CMOS

Chip area 1800*2100μm²

Converters Buck₁

(V_OK1)

Buck₂ (V_OK2)

Boost₁ (V_OT1)

Boost₂ (V_OT2)

Output voltage 1.25V 1.35V 2.0V 2.25V

PWM mode 4mV 3mV

Output

ripples Hysteresis mode 22mV 6mV

Load-regulation 2% 1.5% 1% 0.9%

Line-regulation 0.8%/V 0.55%/V 0.5%/V 0.4%/V

V_OK1 at heavy load NA 0.22% 0.35% 0.31%

VOK2 at heavy load 0.24% NA 0.35% 0.31%

VOT1 at heavy load 0.08% 0.074% NA 0%

Cross- regulation

VOT2 at heavy load 0.16% 0.074% 0.05% NA

PWM mode 90% 93%

Conversion

efficiency Hysteresis mode 80% NA

Chapter 6

Conclusions and Future Works

6.1 Conclusions

In this thesis, the previous techniques of SIMO converter such as state-machine peak current control technique, charge-control (QC) technique, time-multiplex (TM) and PCCM technique, freewheeling current feedback control technique, and OPDC technique has been studied. Since the sub-functions of portable devices need multiple supply voltages are higher or lower than the battery potential, the SIMO converter which can simultaneously provide buck and boost output voltages becomes a very important demand in the field of power IC.

The fundamental behavior of SIMO converter is used to analyze basic controlling sequence and simplify the topology of power structure. To combine the QC and PCCM technique in the minimum number of power switches, the proposed controlling sequence-II evolved into an optimal solution. Without wasting any storage charge in the inductor L, the proposed controlling sequence-II can completely distribute the storage charge among the buck and boost output terminals.

Since the high freewheeling current and long freewheeling period of PCCM technique decrease the power conversion efficiency at light load condition, the load-dependant peak-current (LDPCC) technique is proposed to ensure system stability and minimize the power conversion efficiency at load deviation and light load condition, respectively.

Furthermore, the cross-regulations of buck and boost output terminals are minimized by the dynamic adjustment of LDPCC current level (I_peak). Owing to the proper LDPCC level (I_peak)

adaptively controls the storage charge in form of inductor current (I_L), output terminals can be regulated stably without over- or under-charge issue.

In order to achieve the flexibility of output terminals, the proposed design of control logic has been designed into a repeatable module. According to the required supply voltages of portable device, the control logic can arbitrarily increase or decrease the number of output terminals. Since the used topology of power structure in this thesis has the current accumulation issue during output power of buck terminals is larger than that of boost terminals, the power comparator and delta-voltage generator have been proposed to address the unstable situation. While the boundary condition of current accumulation was detected by power comparator, the extra current path which is path 0 is created by turning on freewheeling switch and buck output switch at the same time. The stability of SIMO converter is achieved, but the large ripple, noise coupling, and low transient response are measured at output terminals.

Furthermore, there has advance circuit in the proposed SIMO converter. The proposed maximum voltage selector not only accurately detects the maximum voltage among supply voltage and output terminals without short through current, but also greatly reduces bias current and transistor number. The flexibility of maximum voltage selector is also achieved.

On the other hand, the voltage spike on node V_X causes the possibility of leakage current and latch up loop during the switching duration of power switches. A novel adaptive body switch (ABS) circuit is proposed to adaptively and rapidly select the highest voltage level between drain and source terminal of power switch. Owing to the simplest structure of ABS circuit, the ultra low power consumption and chip area is achieved.

This thesis proposes a compact-size and high power conversion efficiency SIMO converter for portable device. The proposed SIMO converter with minimized switch transistors utilizes only one inductor component to provide multiple buck and boost output voltages. The energy stored in the inductor can effectively deliver to the buck and boost

output terminals without inductor current accumulation issue. In other words, the proposed hysteresis mode operation and the new delta-voltage generator address the current accumulation issue. Therefore, the proposed SIMO converter not only provides multiple buck and boost output voltages but also minimizes the cross-regulation within 0.35%. Furthermore, owing to the LDPCC technique, the SIMO converter achieves high conversion efficiency from 80% at light load condition to 93% at heavy load condition in the experimental results.

6.2 Future Works

The proposed SIMO converter provides the minimum cross-regulation at multiple buck and boost output terminals and higher power conversion efficiency at light load condition.

The proposed hysteresis mode addresses current accumulation in inductor while the output power of buck output terminals is large than that of boost output terminals. Since those solutions only address the particular issues in the fewer power switches structure. In order to have future works on single inductor structures, there are many challenges on the studies of SIMO converter. Such as that the minimum controlling loops for reducing chip area and power consumption, the fast transient technique for stepping load transition, a new controlling algorithm for adaptive controlling storage charge in the inductor, and the modeling study of SIMO converter.

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