Current Sensor and Charge Reservation Circuits

Fig. 36. The current sensor of [2 and 3] is composed by a fully symmetrical matching structure.

The current sensor shown in Fig. 36 [2 and 3] has a proportional register RS which is N times of the sensing resistor RSEN. The current sensor is composed by a fully symmetrical matching structure. Sufficient accuracy and high bandwidth is used to follow output current variations. To achieve the LDPCC technique, the current sensor cannot be turned off during the whole switching cycle. Thus, the freewheeling power MOSFET as illustrated in Fig. 36 is connected between the input power source VIN and the node VX at the expense of power

conversion efficiency during the freewheeling stage. The current sensor is realized by the matched PMOS transistors M_A2 and M_B2 which are used to enforce the same voltage at node V_x and node V_y. The PMOS transistors M_A2 and M_B2 are biased in the saturation region. Two small and equal biasing current force the PMOS transistors M_A2 and M_B2 to have the same threshold voltage. Self-bias loop is composed by transistors M_A4, M_A3, M_A1, and M_B1. Sensing current is generated via transistor M_B4. The simulation result of current sensor is shown in Fig.

37 and a test pattern of inductor current (I_L) is given by piecewise-linear (PWL) waveform in HSPICE simulation tool. The sensing signal converts the current scale (I_sense) into voltage scale (V_RS) for detecting LDPCC level V_Ipeak. The mirrored current signal (I_sense) is used to charge the indicative capacitors C_IK1~C_IKn and C_IT1~C_ITm of charge reservation circuit which is shown in Fig. 38.

Fig. 37. The simulation result of current sensor.

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Fig. 38. The proposed charge reservation circuits and charge monitor circuit for reducing output ripple.

The architecture of the charge reservation circuit is shown in Fig. 38. The sensing current (I_sense) is converted to the voltage V_RS, which is used to compare with the LDPCC level V_Ipeak as illustrated in Fig. 33. The sensing current (I_sense) is also used to determine the individual

duty cycle of each buck or boost output terminal. Thus, there are n and m charge monitoring circuits in the charge reservation circuit. The indicative capacitors C_IK1~C_IKn and C_IT1~C_ITm are used to monitor the buck and boost output voltages, respectively. The charge monitor circuit in the sub-block is also shown in Fig. 38. When the voltage of driving signal V_SW is set to low, sensing current (I_sense) flows into indicative capacitor C_I to indicate the energy delivering condition of one of buck or boost output voltage. Once the voltage of driving signal V_SW is changed from low to high state, the discharging current (I_in), which comes from the LDPCC circuit, starts to discharge indicative capacitor C_I. Thus, the voltage ripples ΔV_IK1~ΔV_IKn and ΔV_IT1~ΔV_ITm on indicative capacitors C_IK1~C_IKn and C_IT1~C_ITm can monitor the status of the buck and boost output voltages. As a result, the duty cycle can be determined by the voltage V_I on indicative capacitor C_I and the output voltage V_EKi (or V_ETj) of error amplifier array after the operation of comparator array in Fig. 33.

Assume that the value of voltage ripples ΔV_IKi and ΔV_ITj is k_Ki and k_Tj times that of output ripples ΔV_OKi and ΔV_OTj for the buck output terminal i and boost output terminal j, where the suffix i is 1 to n for buck output terminals and the suffix j is 1 to m for boost output terminals.

The buck and boost output ripples ΔV_OKi and ΔV_OTj express as (20) by voltage ripples ΔV_IKi and ΔV_ITj on the indicative capacitors C_IKi and C_ITj in charge reservation circuit.

IKi

The value of voltage ripples ΔV_IKi and ΔV_ITj are set within the input common-mode range of the comparator array in Fig. 33. Besides, the value of inductor current (I_L) is N times that of sensing current (I_sense), which is the sensing current for buck and boost output terminals. Thus, the values of indicative capacitors C_IKi and C_ITj in the charge reservation circuit are given by (21) and (22), respectively.

OTj R_T1~R_Tm in the V-I converters must depend on output load condition. As a result, the charge reservation circuit in the SIMO DC-DC converter can accurately discharge storage charge in indicative capacitors C_IK1~C_IKn and C_IT1~C_ITm. The discharging current sources I_EKi and I_ETj operational trans-conductance amplifier (OTA) can be express as (24) by adopting equation (21).

where G and β_Ki are the trans-conductance of error amplifier and the ratio of voltage divider, respectively. Then, as shown in (25), the discharging current source I_EKi is equal to that the error signal V_EKi is divided by internal resistor R_Ki.

 

Differentiating both sides of (25) by the inductor current (I_L) and setting the value equal to one, (26) is derived to get a discharging current source I_EKi that is proportional to output load current. Consequently, (27) defines the value of resistor R_Ki in charge reservation circuit

for buck output terminals.

Similarly, the value of resistor R_Tj for boost output terminals can be expressed as (28).

ITj ensure that discharging current sources I_EKi and I_ETj in LDPCC circuit are proportional to load current condition of buck and boost output terminals. The discharging current sources I_EKi and I_ETj are expressed as equation (29) and (30) for buck and boost output terminals, respectively.

Ki reservation circuit can accurately decide the duty cycle of the buck or boost output terminals.

The simulation result of charge reservation circuit is shown in Fig. 39. The output signals V_EKi and V_ETj of error amplifier array indicate the output voltage deviation. Since the indicative capacitors C_IKi and C_ITi are charged and discharged by sensing current I_sense and LDPCC circuit sources I_EKi and I_ETj, the voltages V_IKi and V_ITj on indicative capacitors act sensing ripple of output terminals and compare with the output signals V_EKi and V_EKj of error amplifier array for detecting operation duty cycle of each output terminal.

Fig. 39. The simulation result of the proposed charge reservation circuit.

3.3 Logic Control Circuit with Automatic Mode